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1. (WO2019046722) PROVIDING EFFICIENT FLOATING-POINT OPERATIONS USING MATRIX PROCESSORS IN PROCESSOR-BASED SYSTEMS
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Pub. No.: WO/2019/046722 International Application No.: PCT/US2018/049098
Publication Date: 07.03.2019 International Filing Date: 31.08.2018
IPC:
G06F 7/483 (2006.01) ,G06F 7/499 (2006.01) ,G06F 7/544 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
7
Methods or arrangements for processing data by operating upon the order or content of the data handled
38
Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48
using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
483
Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
7
Methods or arrangements for processing data by operating upon the order or content of the data handled
38
Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48
using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
499
Denomination or exception handling, e.g. rounding, overflow
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
7
Methods or arrangements for processing data by operating upon the order or content of the data handled
38
Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
48
using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
544
for evaluating functions by calculation
Applicants:
QUALCOMM INCORPORATED [US/US]; ATTN: International IP Administration 5775 Morehouse Drive San Diego, California 92121-1714, US
Inventors:
HEDDES, Mattheus, Cornelis Antonius Adrianus; US
VAIDHYANATHAN, Natarajan; US
DREYER, Robert; US
VERRILLI, Colin, Beaton; US
BHATTACHARYA, Koustav; US
Agent:
OWENS, Bruce, E. Jr.; US
Priority Data:
16/118,09930.08.2018US
62/552,89031.08.2017US
Title (EN) PROVIDING EFFICIENT FLOATING-POINT OPERATIONS USING MATRIX PROCESSORS IN PROCESSOR-BASED SYSTEMS
(FR) FOURNITURE D'OPÉRATIONS À VIRGULE FLOTTANTE EFFICACES À L'AIDE DE PROCESSEURS MATRICIELS DANS DES SYSTÈMES BASÉS SUR UN PROCESSEUR
Abstract:
(EN) Providing efficient floating-point operations using matrix processors in processor-based systems is disclosed. In this regard, a matrix-processor-based device provides a matrix processor comprising a positive partial sum accumulator and a negative partial sum accumulator. As the matrix processor processes pairs of floating-point operands, the matrix processor calculates an intermediate product based on a first floating-point operand and a second floating-point operand and determines a sign of the intermediate product. Based on the sign, the matrix processor normalizes the intermediate product with a partial sum fraction of the positive partial sum accumulator or the negative partial sum accumulator, then adds the intermediate product to the positive sum accumulator or the negative sum accumulator. After processing all pairs of floating-point operands, the matrix processor subtracts the negative partial sum accumulator from the positive partial sum accumulator to generate a final sum, then renormalizes the final sum a single time.
(FR) L'invention concerne la fourniture d'opérations à virgule flottante efficaces à l'aide de processeurs matriciels dans des systèmes basés sur un processeur. À cet égard, un dispositif basé sur un processeur matriciel fournit un processeur matriciel comprenant un accumulateur de somme partielle positive et un accumulateur de somme partielle négative. Lorsque le processeur matriciel traite des paires d'opérandes à virgule flottante, le processeur matriciel calcule un produit intermédiaire sur la base d'un premier opérande à virgule flottante et d'un second opérande à virgule flottante et détermine un signe du produit intermédiaire. En fonction du signe, le processeur matriciel normalise le produit intermédiaire avec une fraction de somme partielle de l'accumulateur de somme partielle positive ou de l'accumulateur de somme partielle négative, puis ajoute le produit intermédiaire à l'accumulateur de somme positive ou à l'accumulateur de somme négative. Après le traitement de toutes les paires d'opérandes de virgule flottante, le processeur matriciel soustrait l'accumulateur de somme partielle négative de l'accumulateur de somme partielle positive pour générer une somme finale, puis renormalise la somme finale une seule fois.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)