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1. WO2019046402 - METHODS OF PRODUCING SELF-ALIGNED GROWN VIA

Publication Number WO/2019/046402
Publication Date 07.03.2019
International Application No. PCT/US2018/048509
International Filing Date 29.08.2018
IPC
H01L 21/768 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71Manufacture of specific parts of devices defined in group H01L21/7086
768Applying interconnections to be used for carrying current between separate components within a device
CPC
H01J 2237/332
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
2237Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
32Processing objects by plasma generation
33characterised by the type of processing
332Coating
H01J 2237/334
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
2237Discharge tubes exposing object to beam, e.g. for analysis treatment, etching, imaging
32Processing objects by plasma generation
33characterised by the type of processing
334Etching
H01J 37/32715
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
37Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
32Gas-filled discharge tubes, ; e.g. for surface treatment of objects such as coating, plating, etching, sterilising or bringing about chemical reactions
32431Constructional details of the reactor
32715Workpiece holder
H01L 21/02244
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
02104Forming layers
02107Forming insulating materials on a substrate
02225characterised by the process for the formation of the insulating layer
02227formation by a process other than a deposition process
0223formation by oxidation, e.g. oxidation of the substrate
02244of a metallic layer
H01L 21/31055
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
31051Planarisation of the insulating layers
31053involving a dielectric removal step
31055the removal being a chemical etching step, e.g. dry etching
H01L 21/31111
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31105Etching inorganic layers
31111by chemical means
Applicants
  • MICROMATERIALS LLC [US]/[US]
Inventors
  • ZHANG, Ying
  • FREED, Regina
  • INGLE, Nitin K.
  • HWANG, Ho-yung
  • MITRA, Uday
  • MALLICK, Abhijit Basu
Agents
  • WRIGHT, Jonathan B.
Priority Data
62/552,79331.08.2017US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHODS OF PRODUCING SELF-ALIGNED GROWN VIA
(FR) PROCÉDÉS DE PRODUCTION DE TROUS D'INTERCONNEXION DÉVELOPPÉS AUTO-ALIGNÉS
Abstract
(EN)
Methods and apparatus to form fully self-aligned vias are described. Portions of first conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed portions of the first conductive lines and pillars are formed from the first metal film. A second insulating layer is deposited around the pillars. The pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.
(FR)
L'invention concerne des procédés et un appareil pour former des trous d'interconnexion entièrement auto-alignés. Des parties de premières lignes conductrices sont renfoncées dans une première couche isolante sur un substrat. Un premier film métallique est formé dans les parties renfoncées des premières lignes conductrices et des piliers sont formés à partir du premier film métallique. Une seconde couche isolante est déposée autour des piliers. Les piliers sont retirés pour former des trous d'interconnexion dans la seconde couche isolante. Une troisième couche isolante est déposée dans les trous d'interconnexion et une couverture est formée sur la seconde couche isolante. Des parties de la couverture sont sélectivement gravées à partir de la seconde couche isolante pour exposer la seconde couche isolante et les trous d'interconnexion remplis et laissant des parties de la troisième couche isolante sur la seconde couche isolante. La troisième couche isolante est gravée à partir des trous d'interconnexion remplis pour former une ouverture d'interconnexion sur la première ligne conductrice.
Latest bibliographic data on file with the International Bureau