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1. (WO2019046402) METHODS OF PRODUCING SELF-ALIGNED GROWN VIA
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Pub. No.: WO/2019/046402 International Application No.: PCT/US2018/048509
Publication Date: 07.03.2019 International Filing Date: 29.08.2018
IPC:
H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
MICROMATERIALS LLC [US/US]; 2711 Centerville Road, Suite 400 Wilmington, Delaware 19808, US
Inventors:
ZHANG, Ying; US
FREED, Regina; US
INGLE, Nitin K.; US
HWANG, Ho-yung; US
MITRA, Uday; US
MALLICK, Abhijit Basu; US
Agent:
WRIGHT, Jonathan B.; US
Priority Data:
62/552,79331.08.2017US
Title (EN) METHODS OF PRODUCING SELF-ALIGNED GROWN VIA
(FR) PROCÉDÉS DE PRODUCTION DE TROUS D'INTERCONNEXION DÉVELOPPÉS AUTO-ALIGNÉS
Abstract:
(EN) Methods and apparatus to form fully self-aligned vias are described. Portions of first conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed portions of the first conductive lines and pillars are formed from the first metal film. A second insulating layer is deposited around the pillars. The pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.
(FR) L'invention concerne des procédés et un appareil pour former des trous d'interconnexion entièrement auto-alignés. Des parties de premières lignes conductrices sont renfoncées dans une première couche isolante sur un substrat. Un premier film métallique est formé dans les parties renfoncées des premières lignes conductrices et des piliers sont formés à partir du premier film métallique. Une seconde couche isolante est déposée autour des piliers. Les piliers sont retirés pour former des trous d'interconnexion dans la seconde couche isolante. Une troisième couche isolante est déposée dans les trous d'interconnexion et une couverture est formée sur la seconde couche isolante. Des parties de la couverture sont sélectivement gravées à partir de la seconde couche isolante pour exposer la seconde couche isolante et les trous d'interconnexion remplis et laissant des parties de la troisième couche isolante sur la seconde couche isolante. La troisième couche isolante est gravée à partir des trous d'interconnexion remplis pour former une ouverture d'interconnexion sur la première ligne conductrice.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)