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1. (WO2019046192) LOW VOLTAGE REGULATOR
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Pub. No.: WO/2019/046192 International Application No.: PCT/US2018/048145
Publication Date: 07.03.2019 International Filing Date: 27.08.2018
IPC:
G05F 1/575 (2006.01) ,G05F 1/46 (2006.01)
G PHYSICS
05
CONTROLLING; REGULATING
F
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
1
Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
10
Regulating voltage or current
46
wherein the variable actually regulated by the final control device is dc
56
using semiconductor devices in series with the load as final control devices
575
characterised by the feedback circuit
G PHYSICS
05
CONTROLLING; REGULATING
F
SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
1
Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
10
Regulating voltage or current
46
wherein the variable actually regulated by the final control device is dc
Applicants:
XILINX, INC. [US/US]; Attn: Legal Dept. 2100 Logic Drive San Jose, CA 95124, US
Inventors:
IPPILI, Sharat, Babu; US
Agent:
HSU, Frederick; US
HSU, Frederick; US
LIU, Justin; US
Priority Data:
15/693,02831.08.2017US
Title (EN) LOW VOLTAGE REGULATOR
(FR) RÉGULATEUR À FAIBLE TENSION
Abstract:
(EN) Apparatus and method relating to voltage regulation is disclosed. In an apparatus thereof, an integrated circuit (100, 200) includes a first differential opamp (120) having a first gain. The first differential opamp is configured to receive a reference voltage (106) and a feedback voltage (141). A second differential opamp (110) has a second gain less than the first gain. The second differential opamp is configured to receive the reference voltage and the feedback voltage. A driver transistor (104) is configured to provide an output voltage (150) at an output voltage node (140) and to receive a gating voltage (148) output from the second differential opamp. A differential output (121) of the first differential opamp is configured for gating a current source transistor (115) of the second differential opamp. A capacitor (135) is connected to the driver transistor and the current source transistor.
(FR) L'invention concerne un appareil et un procédé se rapportant à la régulation de tension. Dans un appareil associé, un circuit intégré (100, 200) comprend un premier amplificateur opérationnel différentiel (120) ayant un premier gain. Le premier amplificateur opérationnel différentiel est configuré pour recevoir une tension de référence (106) et une tension de rétroaction (141). Un second amplificateur opérationnel différentiel (110) a un second gain inférieur au premier gain. Le second amplificateur opérationnel différentiel est configuré pour recevoir la tension de référence et la tension de rétroaction. Un transistor d'attaque (104) est configuré pour fournir une tension de sortie (150) au niveau d'un nœud de tension de sortie (140) et pour recevoir une tension de déclenchement (148) délivrée par le second amplificateur opérationnel différentiel. Une sortie différentielle (121) du premier amplificateur opérationnel différentiel est configurée pour déclencher un transistor de source de courant (115) du second amplificateur opérationnel différentiel. Un condensateur (135) est connecté au transistor d'attaque et au transistor de source de courant.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)