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1. (WO2019046051) APPARATUSES AND METHODS FOR SHIELDED MEMORY ARCHITECTURE
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Pub. No.: WO/2019/046051 International Application No.: PCT/US2018/047377
Publication Date: 07.03.2019 International Filing Date: 21.08.2018
IPC:
G11C 5/06 (2006.01) ,G11C 7/18 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
5
Details of stores covered by group G11C11/63
06
Arrangements for interconnecting storage elements electrically, e.g. by wiring
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
18
Bit line organisation; Bit line lay-out
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; 8000 South Federal Way Boise, Idaho 83716-9632, US
Inventors:
BEDESCHI, Ferdinando; IT
DI VINCENZO, Umberto; IT
VIMERCATI, Daniele; US
Agent:
ENG, Kimton; US
ENG, Kimton; US
FAUTH D., Justen; US
ANDKEN, Kerry Lee; US
HEGSTROM, Brandon; US
CORDRAY, Michael S.; US
ITO, Mika; US
MA, Yue Matthew; US
MEIKLEJOHN, Paul T.; US
QUECAN, Andrew; US
WETZEL, Elen; US
SPAITH, Jennifer; US
STERN, Ronald; US
Priority Data:
15/691,05530.08.2017US
Title (EN) APPARATUSES AND METHODS FOR SHIELDED MEMORY ARCHITECTURE
(FR) APPAREILS ET PROCÉDÉS D'ARCHITECTURE DE MÉMOIRE PROTÉGÉE
Abstract:
(EN) Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end coupled to a digit line, and a second memory cell including a storage component having a first end coupled to a digit line and a second end coupled to a plate line, wherein the digit line of the second memory cell is adjacent to the plate line of the first memory cell.
(FR) L'invention concerne des appareils et des procédés de mémoire qui comprennent une première cellule de mémoire comprenant un composant de stockage comportant une première extrémité couplée à une ligne de plaque et une seconde extrémité couplée à une ligne de chiffres, et une seconde cellule de mémoire comprenant un composant de stockage comportant une première extrémité couplée à une ligne de chiffres et une seconde extrémité couplée à une ligne de plaque, la ligne de chiffres de la seconde cellule de mémoire étant adjacente à la ligne de plaque de la première cellule de mémoire.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)