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1. (WO2019046050) MEMORY ARRAY RESET READ OPERATION
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Pub. No.: WO/2019/046050 International Application No.: PCT/US2018/047359
Publication Date: 07.03.2019 International Filing Date: 21.08.2018
IPC:
G11C 16/20 (2006.01) ,G11C 16/26 (2006.01) ,G11C 16/04 (2006.01) ,G06F 12/02 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
10
Programming or data input circuits
20
Initialising; Data preset; Chip identification
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
06
Auxiliary circuits, e.g. for writing into memory
26
Sensing or reading circuits; Data output circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
16
Erasable programmable read-only memories
02
electrically programmable
04
using variable threshold transistors, e.g. FAMOS
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
12
Accessing, addressing or allocating within memory systems or architectures
02
Addressing or allocation; Relocation
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; 8000 S. Federal Way Boise, Idaho 83716-9632, US
Inventors:
BINFET, Jeremy; US
HELM, Mark; US
FILIPIAK, William; US
HAWES, Mark; US
Agent:
HARRIS, Philip W.; US
Priority Data:
15/688,64528.08.2017US
Title (EN) MEMORY ARRAY RESET READ OPERATION
(FR) OPÉRATION DE LECTURE DE RÉINITIALISATION DE RÉSEAU DE MÉMOIRE
Abstract:
(EN) Systems, devices, and methods related to reset read are described. A reset read may be employed to initiate a transition of a portion of memory array into a first state or maintain a portion of memory array in a first state, such as a transient state. A reset read may provide a highly-parallelized, energy-efficient option to ensure memory blocks are in the first state. Various modes of reset read may be configured according to different input.
(FR) L'invention concerne des systèmes, des dispositifs et des procédés se rapportant à une lecture de réinitialisation. Une lecture de réinitialisation peut être utilisée pour initier une transition d'une partie du réseau de mémoire dans un premier état ou pour maintenir une partie du réseau de mémoire dans un premier état, tel qu'un état transitoire. Une lecture de réinitialisation peut fournir une option hautement parallélisée et économe en énergie pour garantir que des blocs de mémoire sont dans le premier état. Divers modes de lecture de réinitialisation peuvent être configurés selon différentes entrées.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)