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1. (WO2019046048) MANAGED MULTIPLE DIE MEMORY QOS
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Pub. No.: WO/2019/046048 International Application No.: PCT/US2018/047347
Publication Date: 07.03.2019 International Filing Date: 21.08.2018
IPC:
G06F 3/06 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; 8000 So. Federal Way Boise, Idaho 83716-9632, US
Inventors:
JEAN, Sebastien Andre; US
Agent:
PERDOK, Monique M. / U.S. Reg. No. 42,989; US
ARORA, Suneel; US
BEEKMAN, Marvin L.; US
BLACK, David W.; US
SCHEER, Bradley W.; US
Priority Data:
15/692,22531.08.2017US
Title (EN) MANAGED MULTIPLE DIE MEMORY QOS
(FR) QOS DE MÉMOIRE À PUCES MULTIPLES GÉRÉE
Abstract:
(EN) Devices and techniques for implementing quality-of-service (QoS) parameters in a managed memory device having a number of memory dies are disclosed herein. A memory controller can receive instructions from a host device, determine an initial priority for each instruction using QoS parameters, and allocate the received instructions to the number of memory dies using the initial priority. The memory controller can maintain separate schedules for each of the number or memory dies, update the initial priority for each instruction with the separate schedules, and maintain each of the separate schedules using the updated priority for each instruction in the respective separate schedule.
(FR) L'invention concerne des dispositifs et des techniques pour mettre en œuvre des paramètres de qualité de service (QoS) dans un dispositif à mémoire gérée comprenant un certain nombre de puces de mémoire. Un contrôleur de mémoire peut recevoir des instructions de la part d'un dispositif hôte, déterminer une priorité initiale pour chaque instruction en utilisant des paramètres de QoS et attribuer les instructions reçues au nombre de puces de mémoire en utilisant la priorité initiale. Le contrôleur de mémoire peut maintenir des programmes séparés pour chacun du nombre donné de puces de mémoire, mettre à jour la priorité initiale pour chaque instruction avec les programmes séparés et maintenir chacun des programmes séparés en utilisant la priorité mise à jour pour chaque instruction dans le programme séparé respectif.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)