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1. (WO2019046032) PROCESSING IN MEMORY
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Pub. No.: WO/2019/046032 International Application No.: PCT/US2018/047172
Publication Date: 07.03.2019 International Filing Date: 21.08.2018
IPC:
G06F 13/16 (2006.01) ,G06F 3/06 (2006.01) ,G11C 7/06 (2006.01) ,G11C 7/22 (2006.01) ,G11C 11/4091 (2006.01) ,G11C 11/4076 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
13
Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14
Handling requests for interconnection or transfer
16
for access to memory bus
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
3
Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
06
Digital input from, or digital output to, record carriers
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
06
Sense amplifiers; Associated circuits
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
22
Read-write (R-W) timing or clocking circuits; Read-write (R-W) control signal generators or management
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
401
forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407
for memory cells of the field-effect type
409
Read-write (R-W) circuits
4091
Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
11
Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21
using electric elements
34
using semiconductor devices
40
using transistors
401
forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063
Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407
for memory cells of the field-effect type
4076
Timing circuits
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; Mail Stop 525 8000 South Federal Way P.O. Box 6 Boise, Idaho 83707-0006, US
Inventors:
LEA, Perry V.; US
FINKBEINER, Timothy P.; US
Agent:
KERN, Jacob T.; US
Priority Data:
15/693,37831.08.2017US
Title (EN) PROCESSING IN MEMORY
(FR) TRAITEMENT EN MÉMOIRE
Abstract:
(EN) Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.
(FR) L'invention concerne des appareils et des procédés permettant le traitement en mémoire. Un appareil donné à titre d'exemple comprend un hôte et un dispositif prenant en charge le traitement en mémoire (PIM) couplé à l'hôte par l'intermédiaire d'une interface comprenant un canal de bande latérale. Le dispositif prenant en charge le PIM comprend un réseau de cellules de mémoire couplées à des circuits de détection et est configuré pour effectuer des opérations de vecteur de bits sur des données stockées dans le réseau, et l'hôte comprend un composant de commande PIM pour effectuer une résolution d'adresse virtuelle pour des opérations de PIM avant de fournir un certain nombre d'opérations de vecteur de bits correspondantes au dispositif prenant en charge le PIM par l'intermédiaire du canal de bande latérale.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)