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1. (WO2019045905) APPARATUSES HAVING MEMORY CELLS WITH TWO TRANSISTORS AND ONE CAPACITOR, AND HAVING BODY REGIONS OF THE TRANSISTORS COUPLED WITH REFERENCE VOLTAGES
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Pub. No.: WO/2019/045905 International Application No.: PCT/US2018/043313
Publication Date: 07.03.2019 International Filing Date: 23.07.2018
IPC:
H01L 27/07 (2006.01) ,H01L 27/108 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
06
including a plurality of individual components in a non-repetitive configuration
07
the components having an active region in common
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
108
Dynamic random access memory structures
Applicants:
MICRON TECHNOLOGY, INC. [US/US]; 8000 South Federal Way Boise, ID 83716, US
Inventors:
KARDA, Kamal, M.; US
MOULI, Chandra; US
PULUGURTHA, Srinivas; US
GUPTA, Rajesh, N.; IN
Agent:
MATKIN, Mark, S.; US
HENDRICKSEN, Mark, W.; US
LATWESEN, David, G.; US
SHAURETTE, James, D.; US
GRZELAK, Keith, D.; US
Priority Data:
62/552,99531.08.2017US
Title (EN) APPARATUSES HAVING MEMORY CELLS WITH TWO TRANSISTORS AND ONE CAPACITOR, AND HAVING BODY REGIONS OF THE TRANSISTORS COUPLED WITH REFERENCE VOLTAGES
(FR) APPAREILS AYANT DES CELLULES DE MÉMOIRE COMPORTANT DEUX TRANSISTORS ET UN CONDENSATEUR, ET DONT LES RÉGIONS DE CORPS DES TRANSISTORS SONT COUPLÉES À DES TENSIONS DE RÉFÉRENCE
Abstract:
(EN) Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.
(FR) Certains modes de réalisation de la présente invention concernent une cellule de mémoire comportant deux transistors et un condensateur. Les transistors sont un premier transistor et un second transistor. Le condensateur comprend un premier nœud couplé à une région de source/drain du premier transistor, et comprend un second nœud couplé à une région de source/drain du second transistor. La cellule de mémoire comporte une première région de corps adjacente à la région de source/drain du premier transistor, et comporte une seconde région de corps adjacente à la région de source/drain du second transistor. Une première ligne de connexion de corps couple la première région de corps de la cellule de mémoire à une première tension de référence. Une seconde ligne de connexion de corps couple la seconde région de corps de la cellule de mémoire à une seconde tension de référence. Les première et seconde tensions de référence peuvent être identiques ou différentes.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)