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1. (WO2019045793) SYSTEMS AND METHODS FOR REFRESHING A MEMORY BANK WHILE ACCESSING ANOTHER MEMORY BANK USING A SHARED ADDRESS PATH
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Pub. No.: WO/2019/045793 International Application No.: PCT/US2018/028895
Publication Date: 07.03.2019 International Filing Date: 23.04.2018
IPC:
G11C 8/12 (2006.01) ,G11C 8/06 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
8
Arrangements for selecting an address in a digital store
12
Group selection circuits, e.g. for memory block selection, chip selection, array selection
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
8
Arrangements for selecting an address in a digital store
06
Address interface arrangements, e.g. address buffers
Applicants:
MICRON TECHNOLOGY, INC [US/US]; 8000 South Federal Way Boise, Idaho 83707, US
Inventors:
LEE, Joosang; US
Agent:
MANWARE, Robert A.; US
FLETCHER, Michael G.; US
YODER, Patrick S.; US
POWELL, W. Allen; US
RARIDEN, John M.; US
SWANSON, Tait R.; US
BAKKER, Jila; US
SINCLAIR, JR., Steven J.; US
OSTERHAUS, Matthew G.; US
DOOLEY, Matthew C.; US
HENWOOD, Matthew C.; US
KANTOR, Andrew L.; US
WIMMER, Lance G.; US
BELLAH, Sean J.; US
THOMAS, Jim; US
CORLEY, David; US
Priority Data:
15/692,80431.08.2017US
Title (EN) SYSTEMS AND METHODS FOR REFRESHING A MEMORY BANK WHILE ACCESSING ANOTHER MEMORY BANK USING A SHARED ADDRESS PATH
(FR) SYSTÈMES ET PROCÉDÉS POUR RAFRAÎCHIR UN BLOC MÉMOIRE TOUT EN ACCÉDANT À UN AUTRE BLOC MÉMOIRE À L'AIDE D'UN CHEMIN D'ADRESSE PARTAGÉ
Abstract:
(EN) A system includes first and second sets of memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address input circuit coupled to the address path. The command address input circuit includes a counter that stores and increments the row address. The system also includes a flip-flop that stores the row address in response to receiving a command to refresh the first set of memory banks.
(FR) L'invention concerne un système comprend des premier et second ensembles de blocs mémoire qui stockent des données. Le système comprend également un chemin d'adresse couplé aux blocs mémoire qui fournit une adresse de rangée aux blocs mémoire. Le système comprend en outre un circuit d'entrée d'adresse de commande couplé au chemin d'adresse. Le circuit d'entrée d'adresse de commande comprend un compteur qui stocke et incrémente l'adresse de rangée. Le système comprend également une bascule qui stocke l'adresse de rangée en réponse à la réception d'une commande pour rafraîchir le premier ensemble de blocs mémoire.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)