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1. (WO2019045786) SYSTEMS AND METHODS FOR DATA PATH POWER SAVINGS IN DDR5 MEMORY DEVICES
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/045786 International Application No.: PCT/US2018/027822
Publication Date: 07.03.2019 International Filing Date: 16.04.2018
IPC:
G11C 7/10 (2006.01) ,G11C 8/12 (2006.01) ,G06F 1/32 (2006.01)
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
7
Arrangements for writing information into, or reading information out from, a digital store
10
Input/output (I/O) data interface arrangements, e.g. I/O data control circuits, I/O data buffers
G PHYSICS
11
INFORMATION STORAGE
C
STATIC STORES
8
Arrangements for selecting an address in a digital store
12
Group selection circuits, e.g. for memory block selection, chip selection, array selection
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
1
Details not covered by groups G06F3/-G06F13/82
26
Power supply means, e.g. regulation thereof
32
Means for saving power
Applicants:
MICRON TECHNOLOGY, INC [US/US]; 8000 South Federal Way Boise, Idaho 83707, US
Inventors:
KANDIKONDA, Ravi Kiran; US
Agent:
MANWARE, Robert A.; US
FLETCHER, Michael G.; US
YODER, Patrick S.; US
POWELL, W. Allen; US
RARIDEN, John M.; US
SWANSON, Tait R.; US
BAKKER, Jila; US
SINCLAIR, JR., Steven J.; US
OSTERHAUS, Matthew G.; US
DOOLEY, Matthew C.; US
HENWOOD, Matthew C.; US
KANTOR, Andrew L.; US
WIMMER, Lance G.; US
BELLAH, Sean J.; US
THOMAS, Jim; US
CORLEY, David; US
Priority Data:
15/693,17331.08.2017US
Title (EN) SYSTEMS AND METHODS FOR DATA PATH POWER SAVINGS IN DDR5 MEMORY DEVICES
(FR) SYSTÈMES ET PROCÉDÉS POUR DES ÉCONOMIES D'ÉNERGIE DE CHEMIN DE DONNÉES DANS DES DISPOSITIFS DE MÉMOIRE DDR5
Abstract:
(EN) A memory device includes a data path having a data bus. The memory derive further includes a first one-hot communications interface communicatively coupled to the data bus, and a second one-hot communications interface communicatively coupled to the data bus. The memory device additionally includes at least one memory bank, and an input/output (I/O) interface communicatively coupled to the at least one memory bank via the first one-hot communications interface and the second one-hot communications interface, wherein the first one-hot communications interface is configured to convert a first data pattern received by the I/O interface into one-hot signals transmitted via the data bus to the second one-hot communications interface, and wherein the second one-hot communications interface is configured to convert the one-hot signals into the first data pattern to be stored in the at least one memory bank.
(FR) L'invention concerne un dispositif de mémoire qui comprend un chemin de données comportant un bus de données. Le dispositif de mémoire comprend en outre une première interface de communication 1 parmi n couplée en communication au bus de données, et une seconde interface de communication 1 parmi n couplée en communication au bus de données. Le dispositif de mémoire comprend en outre au moins un bloc mémoire, et une interface d'entrée/sortie (E/S) couplée en communication avec le ou les blocs mémoire par l'intermédiaire de la première interface de communication 1 parmi n et de la seconde interface de communication 1 parmi n, la première interface de communication 1 parmi n étant configurée pour convertir un premier motif de données reçu par l'interface E/S en signaux 1 parmi n transmis par l'intermédiaire du bus de données à la seconde interface de communication 1 parmi n, et la seconde interface de communication 1 parmi n étant configurée pour convertir les signaux 1 parmi n dans le premier motif de données à stocker dans le ou les blocs mémoire.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)