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1. WO2019045785 - ADJUSTING INSTRUCTION DELAYS TO THE LATCH PATH IN DDR5 DRAM

Publication Number WO/2019/045785
Publication Date 07.03.2019
International Application No. PCT/US2018/027819
International Filing Date 16.04.2018
IPC
G11C 7/22 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
7Arrangements for writing information into, or reading information out from, a digital store
22Read-write timing or clocking circuits; Read-write control signal generators or management
G11C 8/12 2006.01
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
8Arrangements for selecting an address in a digital store
12Group selection circuits, e.g. for memory block selection, chip selection, array selection
CPC
G11C 11/4063
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
G11C 11/4082
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
408Address circuits
4082Address Buffers; level conversion circuits
G11C 11/4093
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
11Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
21using electric elements
34using semiconductor devices
40using transistors
401forming cells needing refreshing or charge regeneration, i.e. dynamic cells
4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
407for memory cells of the field-effect type
409Read-write [R-W] circuits 
4093Input/output [I/O] data interface arrangements, e.g. data buffers
G11C 2207/2254
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
2207Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
22Control and timing of internal memory operations
2254Calibration
G11C 29/023
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
023in clock generator or timing circuitry
G11C 29/28
GPHYSICS
11INFORMATION STORAGE
CSTATIC STORES
29Checking stores for correct operation ; ; Subsequent repair; Testing stores during standby or offline operation
04Detection or location of defective memory elements ; , e.g. cell constructio details, timing of test signals
08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
12Built-in arrangements for testing, e.g. built-in self testing [BIST] ; or interconnection details
18Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
26Accessing multiple arrays
28Dependent multiple arrays, e.g. multi-bit arrays
Applicants
  • MICRON TECHNOLOGY, INC [US]/[US]
Inventors
  • WILMOTH, David D.
  • BROWN, Jason M.
Agents
  • MANWARE, Robert A.
  • FLETCHER, Michael G.
  • YODER, Patrick S.
  • POWELL, W. Allen
  • RARIDEN, John M.
  • SWANSON, Tait R.
  • BAKKER, Jila
  • SINCLAIR, JR., Steven J.
  • OSTERHAUS, Matthew G.
  • DOOLEY, Matthew C.
  • HENWOOD, Matthew C.
  • KANTOR, Andrew L.
  • WIMMER, Lance G.
  • BELLAH, Sean J.
  • THOMAS, Jim
  • CORLEY, David
Priority Data
15/691,39430.08.2017US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) ADJUSTING INSTRUCTION DELAYS TO THE LATCH PATH IN DDR5 DRAM
(FR) AJUSTEMENT DE RETARDS D'INSTRUCTION AU CHEMIN DE VERROUILLAGE DANS UNE MÉMOIRE DRAM DDR5
Abstract
(EN)
Memory devices (10) may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device (10) may receive and process signals employing different signal paths that may have different latencies, leading to clock skews. Embodiments discussed herein the application are related to interface circuitry that may decrease certain response times of the memory device (10) by adding delays that minimize the clock skews. For example, a delay in a control path, such as a chip select path, may allow reduction in a delay of an address path, and leading to a decrease of the access time of the memory device (10). Embodiments also disclose how training modes may be employed to further adjust the delays in the control and/or address paths to decrease access times during regular operation.
(FR)
L'invention concerne des dispositifs de mémoire (10) qui peuvent fournir une interface de communication qui est configurée pour recevoir des signaux de commande et/ou des signaux d'adresse provenant de circuits d'utilisateur, tels qu'un processeur. Le dispositif de mémoire (10) peut recevoir et traiter des signaux utilisant différents chemins de signal qui peuvent comporter différentes latences, conduisant à des obliquités d'horloge. Des modes de réalisation de l'invention concernent des circuits d'interface qui peuvent diminuer certains temps de réponse du dispositif de mémoire (10) en ajoutant des retards qui réduisent au minimum les obliquités d'horloge. Par exemple, un retard dans un chemin de commande, tel qu'un chemin de sélection de puce, peut permettre la réduction d'un retard d'un chemin d'adresse, et conduire à une diminution du temps d'accès du dispositif de mémoire (10). Des modes de réalisation concernent également la manière dont des modes d'apprentissage peuvent en outre être utilisés pour ajuster les retards dans les chemins de commande et/ou d'adresse afin de diminuer les temps d'accès pendant un fonctionnement régulier.
Also published as
Latest bibliographic data on file with the International Bureau