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1. (WO2019045763) FABRICATING A DEVICE USING A MULTILAYER STACK
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Pub. No.: WO/2019/045763 International Application No.: PCT/US2017/065018
Publication Date: 07.03.2019 International Filing Date: 07.12.2017
IPC:
H01L 39/24 (2006.01) ,G03F 7/09 (2006.01) ,H01L 21/027 (2006.01) ,H01L 21/3213 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
39
Devices using superconductivity or hyperconductivity; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof
24
Processes or apparatus specially adapted for the manufacture or treatment of devices provided for in group H01L39/135
G PHYSICS
03
PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
F
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
7
Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printed surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
004
Photosensitive materials
09
characterised by structural details, e.g. supports, auxiliary layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
027
Making masks on semiconductor bodies for further photolithographic processing, not provided for in group H01L21/18 or H01L21/34165
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
321
After-treatment
3213
Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
Applicants:
GOOGLE LLC [US/US]; 1600 Amphitheatre Parkway Mountain View, California 94043, US
Inventors:
MEGRANT, Anthony Edward; US
Agent:
VALENTINO, Joseph; US
FRANZ, Paul E.; US
Priority Data:
62/552,74331.08.2017US
Title (EN) FABRICATING A DEVICE USING A MULTILAYER STACK
(FR) FABRICATION D'UN DISPOSITIF À L'AIDE D'UN EMPILEMENT MULTICOUCHE
Abstract:
(EN) A method of fabricating a device is presented. The method includes forming a multilayer stack (101', 102', 103') on a substrate (10', 100') which has a principal surface. The multilayer stack includes a supporting layer (102') formed over the principal surface of the substrate and a photoresist layer (103') formed on the supporting layer, patterning the multilayer stack to form at least one opening such that the photoresist layer is undercut by the supporting layer and anisotropically dry etching the substrate.
(FR) L’invention concerne un procédé de fabrication d’un dispositif. Le procédé consiste à former un empilement multicouche (101', 102', 103') sur un substrat (10', 100') qui a une surface principale. L'empilement multicouche comprend une couche de support (102') formée sur la surface principale du substrat et une couche de résine photosensible (103') formée sur la couche de support, à former en motifs l'empilement multicouche pour former au moins une ouverture de telle sorte que la couche de résine photosensible est contre-dépouillée par la couche de support et à graver à sec de manière anisotrope le substrat.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)