Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019045002) MEMORY DISPLAY DEVICE AND MEMORY DISPLAY DEVICE SYSTEM INCLUDING SAME
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/045002 International Application No.: PCT/JP2018/032192
Publication Date: 07.03.2019 International Filing Date: 30.08.2018
IPC:
G09G 5/00 (2006.01) ,G02F 1/133 (2006.01) ,G09G 3/20 (2006.01) ,G09G 3/36 (2006.01) ,G09G 5/14 (2006.01) ,G09G 5/377 (2006.01) ,G09G 5/393 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
5
Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
34
by control of light from an independent source
36
using liquid crystals
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
5
Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
14
Display of multiple viewports
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
5
Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
36
characterised by the display of individual graphic patterns using a bit-mapped memory
37
Details of the operation on graphic patterns
377
for mixing or overlaying two or more graphic patterns
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
5
Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
36
characterised by the display of individual graphic patterns using a bit-mapped memory
39
Control of the bit-mapped memory
393
Arrangements for updating the contents of the bit-mapped memory
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1 Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
青木 俊也 AOKI Toshiya; --
前田 誠二 MAEDA Seiji; --
Agent:
川上 桂子 KAWAKAMI Keiko; JP
松山 隆夫 MATSUYAMA Takao; JP
Priority Data:
2017-16743631.08.2017JP
Title (EN) MEMORY DISPLAY DEVICE AND MEMORY DISPLAY DEVICE SYSTEM INCLUDING SAME
(FR) DISPOSITIF D’AFFICHAGE DE MÉMOIRE ET SYSTÈME DE DISPOSITIF D'AFFICHAGE DE MÉMOIRE LE COMPRENANT
(JA) メモリ表示デバイスおよびこれを備えたメモリ表示デバイスシステム
Abstract:
(EN) Provided is a memory display device capable of overwriting display data on pixels in one line in a block unit. The memory display device includes: a pixel memory array 14 for storing display data in correspondence with each of a plurality of pixels of a display; a parallel conversion circuit 11 for receiving a serial transmission signal SI from an external host system and extracting the display data corresponding to a predetermined number of pixels in a block unit; a line block selection circuit 12 for writing the display data into the pixel memory array 14 in a block unit in accordance with a writing strobe signal STB; and a sampling circuit 12a for sampling an enable signal ENB. When the enable signal ENB is at a predetermined level, the writing strobe signal STB is enabled.
(FR) L'invention concerne un dispositif d'affichage de mémoire capable d'écraser des données d'affichage sur des pixels dans une ligne dans une unité de bloc. Le dispositif d'affichage de mémoire comprend : un réseau de mémoire de pixels 14 pour stocker des données d'affichage en correspondance avec chacun d'une pluralité de pixels d'un dispositif d'affichage; un circuit de conversion parallèle 11 pour recevoir un signal de transmission série SI provenant d'un système hôte externe et extraire les données d'affichage correspondant à un nombre prédéterminé de pixels dans une unité de bloc; un circuit de sélection de bloc de ligne 12 pour écrire les données d'affichage dans le réseau de mémoire de pixels 14 dans une unité de bloc conformément à un signal stroboscopique d'écriture STB; et un circuit d'échantillonnage pour échantillonner un signal d'activation ENB. Lorsque le signal d'activation ENB est à un niveau prédéterminé, le signal stroboscopique d'écriture STB est activé.
(JA) 一ライン内の画素の表示データをブロック単位で書き換えることが可能なメモリ表示デバイスを提供する。ディスプレイの複数の画素にそれぞれに対応させて表示データを記憶する画素メモリアレイ14と、外部のホストシステムからのシリアル伝送信号SIを受信し、所定の画素数に相当するブロック単位で表示データを抽出するパラレル変換回路11と、書き込みストローブ信号STBに応じて、画素メモリアレイ14へ表示データをブロック単位で書き込むラインブロック選択回路12と、イネーブル信号ENBをサンプリングするサンプリング回路12aとを備え、イネーブル信号ENBが所定のレベルであるときに、書き込みストローブ信号STBを有効とする。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)