Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019044922) SILICON-CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SILICON-CARBIDE SEMICONDUCTOR DEVICE
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/044922 International Application No.: PCT/JP2018/032005
Publication Date: 07.03.2019 International Filing Date: 29.08.2018
IPC:
H01L 29/78 (2006.01) ,H01L 21/205 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/12 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
205
using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
12
characterised by the materials of which they are formed
Applicants:
株式会社デンソー DENSO CORPORATION [JP/JP]; 愛知県刈谷市昭和町1丁目1番地 1-1, Showa-cho, Kariya-city, Aichi 4488661, JP
トヨタ自動車株式会社 TOYOTA JIDOSHA KABUSHIKI KAISHA [JP/JP]; 愛知県豊田市トヨタ町1番地 1, Toyota-cho, Toyota-shi, Aichi 4718571, JP
Inventors:
梶 愛子 KAJI Aiko; JP
竹内 有一 TAKEUCHI Yuichi; JP
箕谷 周平 MITANI Shuhei; JP
鈴木 龍太 SUZUKI Ryota; JP
山下 侑佑 YAMASHITA Yusuke; JP
Agent:
特許業務法人ゆうあい特許事務所 YOU-I PATENT FIRM; 愛知県名古屋市中区錦一丁目6番5号 名古屋錦シティビル4階 Nagoya Nishiki City Bldg. 4F 1-6-5, Nishiki, Naka-ku, Nagoya-shi, Aichi 4600003, JP
Priority Data:
2017-16688331.08.2017JP
Title (EN) SILICON-CARBIDE SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SILICON-CARBIDE SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR AU CARBURE DE SILICIUM ET PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEUR AU CARBURE DE SILICIUM
(JA) 炭化珪素半導体装置およびその製造方法
Abstract:
(EN) A first conductive source region (8) is configured such that a portion thereof on a second conductive base region (6) side has a lower impurity concentration than a portion thereof on the side of the surface which is brought into ohmic contact with a source electrode (15). For example, the source region (8) is configured such that a first source region (8a) has a relatively low concentration and a second source region (8b) has a higher concentration than the first source region. Thus, a saturation current value during load short-circuiting can be reduced, and the short-circuit capacity of this SiC semiconductor device can be increased.
(FR) Un dispositif selon l'invention comprend une première région de source conductrice (8) configurée de telle sorte qu'une partie de celle-ci sur un côté d'une seconde région de base conductrice (6) a une concentration en impuretés inférieure à une partie de celle-ci sur le côté de la surface qui est amenée en contact ohmique avec une électrode de source (15). Par exemple, la région de source (8) est configurée de telle sorte qu'une première région de source (8a) a une concentration relativement faible et une seconde région de source (8b) a une concentration plus élevée que la première région de source. Ainsi, une valeur de courant de saturation pendant un court-circuit de charge peut être réduite, et la capacité de court-circuit de ce dispositif à semi-conducteur au SiC peut être augmentée.
(JA) 第1導電型のソース領域(8)について、第2導電型のベース領域(6)側の方がソース電極(15)にオーミック接触させられる表面側よりも低不純物濃度で構成されるようにする。例えば、ソース領域(8)を、比較的低濃度とされた第1ソース領域(8a)とそれよりも高濃度とされた第2ソース領域(8b)とによって構成する。これにより、負荷短絡時の飽和電流値を小さくすることが可能となり、SiC半導体装置の短絡耐量を向上させることが可能となる。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)