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1. (WO2019044854) VOLTAGE DETECTING CIRCUIT
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Pub. No.: WO/2019/044854 International Application No.: PCT/JP2018/031829
Publication Date: 07.03.2019 International Filing Date: 28.08.2018
IPC:
H02J 7/02 (2016.01) ,G01R 19/00 (2006.01) ,G01R 31/36 (2006.01) ,H01M 10/48 (2006.01)
H ELECTRICITY
02
GENERATION, CONVERSION, OR DISTRIBUTION OF ELECTRIC POWER
J
CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
7
Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
02
for charging batteries from ac mains by converters
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
19
Arrangements for measuring currents or voltages or for indicating presence or sign thereof
G PHYSICS
01
MEASURING; TESTING
R
MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
31
Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
36
Apparatus for testing electrical condition of accumulators or electric batteries, e.g. capacity or charge condition
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
M
PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
10
Secondary cells; Manufacture thereof
42
Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
48
Accumulators combined with arrangements for measuring, testing, or indicating condition, e.g. level or density of the electrolyte
Applicants:
パナソニックIPマネジメント株式会社 PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD. [JP/JP]; 大阪府大阪市中央区城見2丁目1番61号 1-61, Shiromi 2-chome, Chuo-ku, Osaka-shi, Osaka 5406207, JP
パナソニック アジア パシフィック ピーティーイー エルティーディー PANASONIC ASIA PACIFIC PTE. LTD. [SG/SG]; シンガポール、#02-01、ベドック サウス アベニュー1、202 202 Bedok South Avenue 1, #02-01, Singapore, 469332, SG
Inventors:
羽谷 尚久 HATANI, Naohisa; --
森 悟朗 MORI, Gorou; --
Agent:
山尾 憲人 YAMAO, Norihito; JP
川端 純市 KAWABATA, Junichi; JP
Priority Data:
2017-16427629.08.2017JP
Title (EN) VOLTAGE DETECTING CIRCUIT
(FR) CIRCUIT DE DÉTECTION DE TENSION
(JA) 電圧検出回路
Abstract:
(EN) A voltage detecting circuit of the present invention measures each cell voltage of an assembled battery configured by connecting a plurality of cells in series. With a voltage detecting circuit as a first voltage detecting circuit, the voltage detecting circuit comprises: a downstream-side communication circuit that performs communication with a host device that performs communication with a plurality of voltage detecting circuits connected to each other in series; an upstream-side communication circuit that performs communication with a third voltage detecting circuit provided further to the upstream side than the first voltage detecting circuit; a reply signal generating circuit that generates a reply signal containing data detected by the first voltage detecting circuit; an upstream-side transfer circuit that transfers signals received by the upstream-side communication circuit to the downstream side; a dummy current consumption circuit that consumes a dummy current; and a control circuit that performs control to selectively operate one of the reply signal generating circuit, the upstream-side transfer circuit, and the dummy current consumption circuit on the basis of a communication command signal received from the host device.
(FR) La présente invention concerne un circuit de détection de tension qui mesure chaque tension d'élément d'une batterie assemblée configurée par connexion d'une pluralité d'éléments en série. En tant que premier circuit de détection de tension, le circuit de détection de tension comprend : un circuit de communication côté aval qui effectue une communication avec un dispositif hôte qui réalise une communication avec une pluralité de circuits de détection de tension connectés en série les uns avec les autres ; un circuit de communication côté amont qui effectue une communication avec un troisième circuit de détection de tension placé plus loin du côté amont que le premier circuit de détection de tension ; un circuit de génération de signal de réponse qui génère un signal de réponse contenant des données détectées par le premier circuit de détection de tension ; un circuit de transfert côté amont qui transfère des signaux reçus par le circuit de communication côté amont vers le côté aval ; un circuit de consommation de courant fictif qui consomme un courant fictif ; et un circuit de commande qui effectue une commande de manière à faire fonctionner sélectivement le circuit de génération de signal de réponse ou le circuit de transfert côté amont ou le circuit de consommation de courant fictif sur la base d'un signal de commande de communication reçu du dispositif hôte.
(JA) 本発明にかかる電圧検出回路は、複数のセルを直列に接続して構成される組電池の各セル電圧を測定する。電圧検出回路を第1の電圧検出回路とし、電圧検出回路は、互いに直列に接続された複数の電圧検出回路と通信を行うホスト装置と通信を行う下流側通信回路と、第1の電圧検出回路よりも上流側に設けられた第3の電圧検出回路と通信を行う上流側通信回路と、第1の電圧検出回路により検出されたデータを含むリプライ信号を発生するリプライ信号発生回路と、上流側通信回路により受信された信号を下流側に転送する上流側転送回路と、ダミー電流を消費するダミー電流消費回路と、ホスト装置から受信した通信コマンドの信号に基づいて、リプライ信号発生回路と、上流側転送回路と、ダミー電流消費回路とのうちのいずれか1つを選択的に動作させるように制御する制御回路とを備える。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)