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1. (WO2019044798) METHOD FOR MANUFACTURING POWER SEMICONDUCTOR DEVICE, SHEET FOR HOT PRESSING, AND THERMOSETTING RESIN COMPOSITION FOR HOT PRESSING
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Pub. No.: WO/2019/044798 International Application No.: PCT/JP2018/031678
Publication Date: 07.03.2019 International Filing Date: 28.08.2018
IPC:
H01L 21/52 (2006.01) ,H01L 25/07 (2006.01) ,H01L 25/18 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
50
Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/06-H01L21/326162
52
Mounting semiconductor bodies in containers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
Applicants:
日立化成株式会社 HITACHI CHEMICAL COMPANY, LTD. [JP/JP]; 東京都千代田区丸の内一丁目9番2号 9-2, Marunouchi 1-chome, Chiyoda-ku, Tokyo 1006606, JP
Inventors:
小関 裕太 KOSEKI Yuta; JP
本田 一尊 HONDA Kazutaka; JP
Agent:
長谷川 芳樹 HASEGAWA Yoshiki; JP
清水 義憲 SHIMIZU Yoshinori; JP
平野 裕之 HIRANO Hiroyuki; JP
Priority Data:
2017-16340728.08.2017JP
2018-13143511.07.2018JP
Title (EN) METHOD FOR MANUFACTURING POWER SEMICONDUCTOR DEVICE, SHEET FOR HOT PRESSING, AND THERMOSETTING RESIN COMPOSITION FOR HOT PRESSING
(FR) PROCÉDÉ DE FABRICATION D'UN DISPOSITIF À SEMI-CONDUCTEUR DE PUISSANCE, FEUILLE POUR PRESSAGE À CHAUD, ET COMPOSITION DE RÉSINE THERMODURCISSABLE POUR PRESSAGE À CHAUD
(JA) パワー半導体装置を製造する方法、熱プレス用シート及び熱プレス用熱硬化性樹脂組成物
Abstract:
(EN) Disclosed is a method for manufacturing a power semiconductor device provided with a wiring board and a power semiconductor element mounted on the wiring board. This method comprises a step in which a laminate having a wiring board, a power semiconductor element, and a metal particle-containing sintered material is heated and pressed by being sandwiched between a stage and a crimping head, and thereby a wiring layer and an electrode are electrically connected via a sintered metal layer formed by sintering the sintered material. The laminate is heated and pressed in a state in which a sheet that is for hot pressing and has a thermosetting resin layer is disposed between the laminate and the crimping head.
(FR) L'invention concerne un procédé de fabrication d'un dispositif semi-conducteur de puissance pourvu d'une carte de câblage et d'un élément à semi-conducteur de puissance monté sur la carte de câblage. Ce procédé comprend une étape dans laquelle un stratifié ayant une carte de câblage, un élément à semi-conducteur de puissance et un matériau fritté contenant des particules métalliques est chauffé et pressé en étant pris en sandwich entre un étage et une tête de sertissage, une couche de câblage et une électrode étant ainsi électriquement connectées par l'intermédiaire d'une couche métallique frittée formée par frittage du matériau fritté. Le stratifié est chauffé et pressé à un état dans lequel une feuille qui est destinée à être pressée à chaud et comporte une couche de résine thermodurcissable est disposée entre le stratifié et la tête de sertissage.
(JA) 配線基板及び該配線基板に搭載されたパワー半導体素子を備えるパワー半導体装置を製造する方法が開示される。当該方法は、配線基板とパワー半導体素子と金属粒子を含む焼結材とを有する積層体を、ステージ及び圧着ヘッドで挟むことによって加熱及び加圧し、それにより、焼結材の焼結により形成された焼結金属層を介して配線層と電極とを電気的に接続する工程を備える。積層体と圧着ヘッドとの間に、熱硬化性樹脂層を有する熱プレス用シートを介在させた状態で、積層体が加熱及び加圧される。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)