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1. (WO2019044748) SEMICONDUCTOR MODULE AND ELECTRIC POWER CONVERTER
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Pub. No.: WO/2019/044748 International Application No.: PCT/JP2018/031521
Publication Date: 07.03.2019 International Filing Date: 27.08.2018
IPC:
H01L 25/07 (2006.01) ,H01L 25/18 (2006.01) ,H02M 7/48 (2007.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
03
all the devices being of a type provided for in the same subgroup of groups H01L27/-H01L51/128
04
the devices not having separate containers
07
the devices being of a type provided for in group H01L29/78
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
H ELECTRICITY
02
GENERATION, CONVERSION, OR DISTRIBUTION OF ELECTRIC POWER
M
APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
7
Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
42
Conversion of dc power input into ac power output without possibility of reversal
44
by static converters
48
using discharge tubes with control electrode or semiconductor devices with control electrode
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
中嶋 純一 NAKASHIMA, Junichi; JP
森崎 翔太 MORISAKI, Shota; JP
玉田 美子 TAMADA, Yoshiko; JP
中山 靖 NAKAYAMA, Yasushi; JP
根岸 哲 NEGISHI, Tetsu; JP
津田 亮 TSUDA, Ryo; JP
林田 幸昌 HAYASHIDA, Yukimasa; JP
伊達 龍太郎 DATE, Ryutaro; JP
Agent:
特許業務法人深見特許事務所 FUKAMI PATENT OFFICE, P.C.; 大阪府大阪市北区中之島三丁目2番4号 中之島フェスティバルタワー・ウエスト Nakanoshima Festival Tower West, 2-4, Nakanoshima 3-chome, Kita-ku, Osaka-shi, Osaka 5300005, JP
Priority Data:
2017-16944604.09.2017JP
Title (EN) SEMICONDUCTOR MODULE AND ELECTRIC POWER CONVERTER
(FR) MODULE À SEMI-CONDUCTEURS ET CONVERTISSEUR DE COURANT ÉLECTRIQUE
(JA) 半導体モジュール及び電力変換装置
Abstract:
(EN) According to the present invention, gates of a plurality of semiconductor switching elements (12) are electrically connected to a common gate control pattern (10) by means of wires (15); and sources of the plurality of semiconductor switching elements (12) are electrically connected to a common source control pattern (11) by means of wires (16). Since the gate control pattern (10) is arranged so as to sandwich the source control pattern (11) between itself and the plurality of semiconductor switching elements (12), which are connected in parallel and operate in parallel, the wires (15) are longer than the wires (16) and have higher inductances than the wires (16). Consequently, gate oscillation of the plurality of semiconductor switching elements (12), which are connected in parallel and operate in parallel, are reduced or suppressed.
(FR) Selon la présente invention, des grilles d'une pluralité d'éléments de commutation à semi-conducteurs (12) sont électriquement connectées à un motif de commande de grille commun (10) au moyen de fils (15) ; et des sources de la pluralité d'éléments de commutation à semi-conducteurs (12) sont électriquement connectées à un motif de commande de source commun (11) au moyen de fils (16). Comme le motif de commande de grille (10) est agencé de manière à prendre en sandwich le motif de commande de source (11) entre lui-même et la pluralité d'éléments de commutation à semi-conducteurs (12), qui sont connectés en parallèle et fonctionnent en parallèle, les fils (15) sont plus longs que les fils (16) et ont des inductances plus élevées que les fils (16). Par conséquent, l'oscillation de grille de la pluralité d'éléments de commutation à semi-conducteurs (12), qui sont connectés en parallèle et fonctionnent en parallèle, est réduite ou supprimée.
(JA) 複数の半導体スイッチング素子(12)のゲートは、ワイヤ(15)によって共通のゲート制御パターン(10)と電気的に接続される。複数の半導体スイッチング素子(12)のソースは、ワイヤ(16)によって共通のソース制御パターン(11)と電気的に接続される。ゲート制御パターン(10)は、並列接続されて並列動作する複数の半導体スイッチング素子(12)に対して、ソース制御パターン(11)を挟んで配置されるので、ワイヤ(15)は、ワイヤ(16)よりも長くなり、ワイヤ(16)よりも大きいインダクタンスを有する。これにより、並列接続されて並列動作する複数の半導体スイッチング素子(12)におけるゲート発振を軽減又は抑制する。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)