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1. (WO2019044706) SUBSTRATE FOR MOUNTING ELECTRONIC COMPONENTS, ELECTRONIC DEVICE, AND ELECTRONIC MODULE
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Pub. No.: WO/2019/044706 International Application No.: PCT/JP2018/031376
Publication Date: 07.03.2019 International Filing Date: 24.08.2018
IPC:
H01L 33/62 (2010.01) ,H01L 23/12 (2006.01) ,H05K 3/46 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
48
characterised by the semiconductor body packages
62
Arrangements for conducting electric current to or from the semiconductor body, e.g. leadframe, wire-bond or solder balls
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
12
Mountings, e.g. non-detachable insulating substrates
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
Applicants:
京セラ株式会社 KYOCERA CORPORATION [JP/JP]; 京都府京都市伏見区竹田鳥羽殿町6番地 6, Takeda Tobadono-cho, Fushimi-ku, Kyoto-shi, Kyoto 6128501, JP
Inventors:
福薗 茂義 FUKUZONO,Shigeyoshi; JP
馬場 祐貴 BABA,Yuuki; JP
Priority Data:
2017-16445329.08.2017JP
Title (EN) SUBSTRATE FOR MOUNTING ELECTRONIC COMPONENTS, ELECTRONIC DEVICE, AND ELECTRONIC MODULE
(FR) SUBSTRAT POUR MONTAGE DE COMPOSANTS ÉLECTRONIQUES, DISPOSITIF ÉLECTRONIQUE, ET MODULE ÉLECTRONIQUE
(JA) 電子部品搭載用基板、電子装置および電子モジュール
Abstract:
(EN) A substrate for mounting electronic components has: an insulating substrate for mounting electronic components; a via conductor positioned in the thickness direction inside the insulating substrate; and a via pad conductor that is positioned inside the insulating substrate, is connected to the via conductor, has gradually increasing thickness from the outer edge part toward the inside, and includes protruding parts that protrude from the via conductor in the width direction of the via conductor.
(FR) La présente invention concerne un substrat pour montage de composants électroniques qui comprend : un substrat isolant permettant de monter des composants électroniques ; un conducteur de trou d'interconnexion positionné dans le sens de l'épaisseur à l'intérieur du substrat isolant ; et un conducteur de contact à trou d'interconnexion qui est positionné à l'intérieur du substrat isolant, est connecté au conducteur de trou d'interconnexion, a une épaisseur graduellement croissante de la partie de bord externe vers l'intérieur, et comprend des parties en saillie qui font saillie depuis le conducteur de trou d'interconnexion dans le sens de la largeur du conducteur de trou d'interconnexion.
(JA) 電子部品搭載用基板は、電子部品を搭載する絶縁基板と、絶縁基板の内部で、厚み方向に位置したビア導体と、絶縁基板の内部に位置し、ビア導体に接続され、外縁部から内側に向かって厚みが漸次大きくなっており、ビア導体の幅方向において、ビア導体から突出した突出部を含んでいるビアパッド導体とを有している。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)