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1. (WO2019044705) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME
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Pub. No.: WO/2019/044705 International Application No.: PCT/JP2018/031369
Publication Date: 07.03.2019 International Filing Date: 24.08.2018
IPC:
H01L 21/822 (2006.01) ,H01L 27/04 (2006.01) ,H01L 27/10 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
Applicants:
国立大学法人静岡大学 NATIONAL UNIVERSITY CORPORATION SHIZUOKA UNIVERSITY [JP/JP]; 静岡県静岡市駿河区大谷836 836, Ohya, Suruga-ku, Shizuoka-shi, Shizuoka 4228529, JP
Inventors:
丹沢 徹 TANZAWA Toru; JP
Agent:
長谷川 芳樹 HASEGAWA Yoshiki; JP
諏澤 勇司 SUZAWA Yuji; JP
Priority Data:
2017-16881401.09.2017JP
Title (EN) SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR SAME
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体装置及びその製造方法
Abstract:
(EN) A nonvolatile memory device 1 comprises: a semiconductor substrate 3; a memory array area 5 having a plurality of memory cells 13, a plurality of straight word lines 11 which follow along a plane at a height h1 above the semiconductor substrate 3, and a plurality of straight bit lines 15 which are formed along a plane at a height h2 above the semiconductor substrate 3 in the direction intersecting with the word lines 11, wherein the plurality of memory cells 13 are provided between the plurality of bit lines 15 and intersections 17 at which the plurality of word lines 11 and the plurality of bit lines 15 respectively intersect; and a periphery circuit area 7 having a plurality of straight linear electrodes 19 formed along the plane at the height h1 above the semiconductor substrate 3, a plurality of straight linear electrodes 21 formed in a direction intersecting with the linear electrodes 19 along the plane at the height h2 above the semiconductor substrate 3, and insulating bodies 23 positioned at least between the linear electrodes 19 and the linear electrodes 21.
(FR) Cette invention concerne un dispositif de mémoire non volatile (1), comprenant : un substrat semi-conducteur (3) ; une zone de matrice de mémoire (5) ayant une pluralité de cellules de mémoire (13), une pluralité de lignes de mots droites (11) qui suivent un plan à une hauteur (h1) au-dessus du substrat semi-conducteur (3), et une pluralité de lignes de bit droites (15) qui sont formées le long d'un plan à une hauteur (h2) au-dessus du substrat semi-conducteur (3) dans la direction croisant les lignes de mots (11), la pluralité de cellules de mémoire (13) étant disposées entre la pluralité de lignes de bits (15) et des intersections (17) auxquelles la pluralité de lignes de mots (11) et la pluralité de lignes de bits (15) se croisent respectivement ; et une zone de circuit périphérique (7) ayant une pluralité d'électrodes linéaires droites (19) formées le long du plan à la hauteur (h1) au-dessus du substrat semi-conducteur (3), une pluralité d'électrodes linéaires droites (21) formées dans une direction croisant les électrodes linéaires (19) le long du plan à la hauteur (h2) au-dessus du substrat semi-conducteur (3), et des corps isolants (23) positionnés au moins entre les électrodes linéaires (19) et les électrodes linéaires (21).
(JA) 不揮発性メモリ装置1は、半導体基板3と、半導体基板3上の高さh1の面に沿って直線状の複数のワード線11、半導体基板3上の高さh2の面に沿ってワード線11に交差する方向に形成された直線状の複数のビット線15、及び複数のワード線11のそれぞれにおける複数のビット線15との交差部17と、複数のビット線15のそれぞれとの間に設けられた複数のメモリセル13を有するメモリアレイ領域5と、半導体基板3上の高さh1の面に沿って形成された直線状の複数の線状電極19、半導体基板3上の高さh2の面に沿って線状電極19に交差する方向に形成された直線状の複数の線状電極21、及び線状電極19と線状電極21との間に少なくとも配置された絶縁体23を有する周辺回路領域7とを備える。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)