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1. (WO2019044686) SEMICONDUCTOR LAMINATE, LIGHT-RECEIVING ELEMENT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR LAMINATE
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Pub. No.: WO/2019/044686 International Application No.: PCT/JP2018/031313
Publication Date: 07.03.2019 International Filing Date: 24.08.2018
IPC:
H01L 31/10 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
31
Semiconductor devices sensitive to infra-red radiation, light, electromagnetic radiation of shorter wavelength, or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
08
in which radiation controls flow of current through the device, e.g. photoresistors
10
characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
Applicants:
住友電気工業株式会社 SUMITOMO ELECTRIC INDUSTRIES, LTD. [JP/JP]; 大阪府大阪市中央区北浜四丁目5番33号 5-33, Kitahama 4-chome, Chuo-ku, Osaka-shi, Osaka 5410041, JP
Inventors:
冬木 琢真 FUYUKI Takuma; JP
土井 友博 DOI Tomohiro; JP
呉 剛志 GO Takashi; JP
石塚 貴司 ISHIZUKA Takashi; JP
Agent:
中田 元己 NAKATA Motomi; JP
森田 剛史 MORITA Takeshi; JP
高城 政浩 TAKAGI Masahiro; JP
緒方 大介 OGATA Daisuke; JP
久貝 裕一 KUGAI Hirokazu; JP
Priority Data:
2017-16897101.09.2017JP
Title (EN) SEMICONDUCTOR LAMINATE, LIGHT-RECEIVING ELEMENT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR LAMINATE
(FR) STRATIFIÉ SEMI-CONDUCTEUR, ÉLÉMENT DE RÉCEPTION DE LUMIÈRE ET PROCÉDÉ DE FABRICATION DE STRATIFIÉ SEMI-CONDUCTEUR
(JA) 半導体積層体、受光素子および半導体積層体の製造方法
Abstract:
(EN) A semiconductor laminate, provided with a substrate comprising a group III-V compound semiconductor, and a quantum well structure disposed on the substrate. The quantum well structure includes: a second element layer comprising a group III-V compound semiconductor and containing Sb; and a first element layer disposed so as to be in contact with the second element layer, the first element layer comprising a group III-V compound semiconductor. In the first element layer, the thickness corresponding to the Sb content decreasing from 80% to 6% of the maximum value of the Sb content of the second element layer, in the direction moving away from the substrate, is 0.5 to 3.0 nm (inclusive).
(FR) L'invention concerne un stratifié semi-conducteur, comprenant un substrat comprenant un semi-conducteur composite du groupe III-V, et une structure de puits quantique disposée sur le substrat. La structure de puits quantique comprend : une seconde couche d'élément comprenant un semi-conducteur composite du groupe III-V et contenant du Sb ; et une première couche d'élément disposée de manière à être en contact avec la seconde couche d'élément, la première couche d'élément comprenant un semi-conducteur composite du groupe III-V. Dans la première couche d'élément, l'épaisseur correspondant à la teneur en Sb diminuant de 80 % à 6 % de la valeur maximale de la teneur en Sb de la seconde couche d'élément, dans la direction s'éloignant du substrat, est de 0,5 à 3,0 nm (inclus).
(JA) 半導体積層体は、III-V族化合物半導体からなる基板と、基板上に配置される量子井戸構造と、を備える。量子井戸構造は、III-V族化合物半導体からなり、Sbを含有する第2要素層と、第2要素層上に接触して配置され、III-V族化合物半導体からなる第1要素層と、を含む。第1要素層の基板から離れる向きにおいて、Sbの含有量が第2要素層におけるSbの含有量の最大値の80%から前記最大値の6%にまで減少するまでの厚みが0.5nm以上3.0nm以下である。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)