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1. (WO2019044546) ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE
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Pub. No.: WO/2019/044546 International Application No.: PCT/JP2018/030540
Publication Date: 07.03.2019 International Filing Date: 17.08.2018
IPC:
G09G 3/36 (2006.01) ,G02F 1/133 (2006.01) ,G02F 1/1368 (2006.01) ,G09G 3/20 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
34
by control of light from an independent source
36
using liquid crystals
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
Applicants:
シャープ株式会社 SHARP KABUSHIKI KAISHA [JP/JP]; 大阪府堺市堺区匠町1番地 1, Takumi-cho, Sakai-ku, Sakai City, Osaka 5908522, JP
Inventors:
山本 薫 YAMAMOTO Kaoru; --
Agent:
奥田 誠司 OKUDA Seiji; JP
Priority Data:
2017-16415629.08.2017JP
Title (EN) ACTIVE MATRIX SUBSTRATE AND DISPLAY DEVICE
(FR) SUBSTRAT À MATRICE ACTIVE ET DISPOSITIF D'AFFICHAGE
(JA) アクティブマトリクス基板および表示装置
Abstract:
(EN) An active matrix substrate is provided with a demultiplexer circuit provided on the periphery. Each simple circuit in the demultiplexer circuit distributes a display signal from one signal output line to n source bus lines (n is an integer of 2 or greater). Each simple circuit includes n branch lines and n switching TFTs for individually controlling the on and off of electrical connections between the branch lines and the source bus lines. The demultiplexer circuit includes a plurality of booster circuits capable of increasing the voltage applied to the gate electrode of the switching TFT. Each booster circuit includes: a set-and-reset unit that performs a set operation for pre-charging a node connected to a gate electrode and a reset operation for resetting the potential of the node at mutually different times; and a booster unit that boosts the potential of the node pre-charged by the set operation.
(FR) L'invention concerne un substrat de matrice active pourvu d'un circuit démultiplexeur disposé à la périphérie. Chaque circuit unitaire du circuit démultiplexeur distribue un signal d'affichage d'une ligne de sortie de signal vers n lignes de bus source (n étant un entier supérieur ou égal à 2). Chaque circuit simple comprend n lignes de dérivation et n transistors TFT de commutation permettant de commander individuellement l'activation et la désactivation de connexions électriques, entre les lignes de dérivation et les lignes de bus source. Le circuit démultiplexeur comprend une pluralité de circuit survolteurs, susceptibles d'amplifier la tension appliquée à l'électrode de grille des TFT de commutation. Chaque circuit survolteur comprend : une unité d'initialisation et de réinitialisation, qui effectue une opération d'initialisation, permettant de précharger un nœud connecté à une électrode de grille, et une opération de réinitialisation, permettant de réinitialiser le potentiel du nœud à des instants mutuellement différents; et une unité d'amplification, qui amplifie le potentiel du nœud préchargé par l'opération d'initialisation.
(JA) アクティブマトリクス基板は、周辺領域に配置されたデマルチプレクサ回路を備える。デマルチプレクサ回路の各単位回路は、1本の信号出力線からn本(nは2以上の整数)のソースバスラインに表示信号を分配する。各単位回路は、n本の分岐配線と、分岐配線とソースバスラインとの電気的な接続を個別にオン/オフ制御するn個のスイッチングTFTとを含む。デマルチプレクサ回路は、スイッチングTFTのゲート電極に印加される電圧を昇圧し得る複数個のブースト回路を含む。各ブースト回路は、ゲート電極に接続されたノードをプリチャージするセット動作およびノードの電位をリセットするリセット動作を互いに異なるタイミングで行うセット・リセット部と、セット動作によってプリチャージされたノードの電位を昇圧するブースト動作を行うブースト部とを含む。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)