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1. (WO2019044425) MULTILAYER SUBSTRATE AND ANTENNA MODULE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/044425 International Application No.: PCT/JP2018/029610
Publication Date: 07.03.2019 International Filing Date: 07.08.2018
IPC:
H05K 1/02 (2006.01) ,H01P 5/08 (2006.01) ,H01Q 13/08 (2006.01) ,H01Q 21/06 (2006.01) ,H01Q 23/00 (2006.01) ,H05K 1/16 (2006.01) ,H05K 3/40 (2006.01) ,H05K 3/46 (2006.01)
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
02
Details
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
P
WAVEGUIDES; RESONATORS, LINES OR OTHER DEVICES OF THE WAVEGUIDE TYPE
5
Coupling devices of the waveguide type
08
for linking lines or devices of different kinds
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
Q
AERIALS
13
Waveguide horns or mouths; Slot aerials; Leaky-waveguide aerials; Equivalent structures causing radiation along the transmission path of a guided wave
08
Radiating ends of two-conductor microwave transmission lines, e.g. of coaxial lines, of microstrip lines
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
Q
AERIALS
21
Aerial arrays or systems
06
Arrays of individually energised aerial units similarly polarised and spaced apart
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
Q
AERIALS
23
Aerials with active circuits or circuit elements integrated within them or attached to them
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
1
Printed circuits
16
incorporating printed electric components, e.g. printed resistor, capacitor, inductor
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
40
Forming printed elements for providing electric connections to or between printed circuits
H ELECTRICITY
05
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
K
PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
3
Apparatus or processes for manufacturing printed circuits
46
Manufacturing multi-layer circuits
Applicants:
株式会社村田製作所 MURATA MANUFACTURING CO., LTD. [JP/JP]; 京都府長岡京市東神足1丁目10番1号 10-1, Higashikotari 1-chome, Nagaokakyo-shi, Kyoto 6178555, JP
Inventors:
有海 仁章 ARIUMI, Saneaki; JP
Agent:
吉川 修一 YOSHIKAWA, Shuichi; JP
傍島 正朗 SOBAJIMA, Masaaki; JP
Priority Data:
2017-16513030.08.2017JP
Title (EN) MULTILAYER SUBSTRATE AND ANTENNA MODULE
(FR) SUBSTRAT MULTICOUCHE ET MODULE D'ANTENNE
(JA) 多層基板及びアンテナモジュール
Abstract:
(EN) A multilayer substrate (14) comprises: a plurality of insulator layers that are laminated; and a conductor post (143) that passes through two or more insulator layers (411 and 412) among a plurality of insulator layers. The conductor post (143) has a via conductor (311) that passes through the insulator layer (411), and a via conductor (312) that passes through the insulator layer (412) adjacent to the insulator layer (411). The via conductor (311) and the via conductor (312) respectively have a tapered shape for which the cross section becomes smaller from one end part toward the other end part in the lamination direction of the plurality of insulator layers. The via conductor (311) and the via conductor (312) have large diameter parts (311L and 312L), which are the end parts for which the cross section is larger, directly joined to each other, or small diameter parts (311S and 312S), which are the end parts for which the cross section is smaller, directly joined to each other.
(FR) Cette invention concerne un substrat multicouche (14), comprenant : une pluralité de couches isolantes qui sont stratifiées ; et un plot conducteur (143) qui traverse au moins deux couches isolantes (411 et 412) parmi une pluralité de couches isolantes. Le plot conducteur (143) comporte un conducteur d'interconnexion (311) qui traverse la couche isolante (411), et un conducteur d'interconnexion (312) qui traverse la couche isolante (412) adjacente à la couche isolante (411). Le conducteur d'interconnexion (311) et le conducteur d'interconnexion (312) ont respectivement une forme effilée pour laquelle la section transversale diminue d'une partie d'extrémité vers l'autre partie d'extrémité dans la direction de stratification de la pluralité de couches isolantes. Le conducteur d'interconnexion (311) et le conducteur d'interconnexion (312) ont des parties de grand diamètre (311L et 312L), qui sont les parties d'extrémité dont la section transversale est plus grande, directement reliées l'une à l'autre, ou des parties de petit diamètre (311S et 312S), qui sont les parties d'extrémité dont la section transversale est plus petite, directement reliées l'une à l'autre.
(JA) 多層基板(14)は、積層された複数の絶縁体層と、複数の絶縁体層のうち2以上の絶縁体層(411及び412)を貫通する導体柱(143)と、を備え、導体柱(143)は、絶縁体層(411)を貫通するビア導体(311)と、絶縁体層(411)に隣り合う絶縁体層(412)を貫通するビア導体(312)と、を有し、ビア導体(311)及びビア導体(312)のそれぞれは、複数の絶縁体層の積層方向において一方の端部から他方の端部にかけて断面が小さくなるテーパー形状を有し、ビア導体(311)とビア導体(312)とは、断面が大きい端部である大径部(311L及び312L)同士または断面が小さい端部である小径部(311S及び312S)同士が直接接合されている。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)