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1. (WO2019044301) SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
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Pub. No.: WO/2019/044301 International Application No.: PCT/JP2018/028118
Publication Date: 07.03.2019 International Filing Date: 26.07.2018
IPC:
H01L 21/336 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
ソニーセミコンダクタソリューションズ株式会社 SONY SEMICONDUCTOR SOLUTIONS CORPORATION [JP/JP]; 神奈川県厚木市旭町四丁目14番1号 4-14-1, Asahi-cho, Atsugi-shi, Kanagawa 2430014, JP
Inventors:
江尻 洋一 EJIRI, Hirokazu; JP
Agent:
亀谷 美明 KAMEYA, Yoshiaki; JP
金本 哲男 KANEMOTO, Tetsuo; JP
萩原 康司 HAGIWARA, Yasushi; JP
Priority Data:
2017-16681631.08.2017JP
Title (EN) SEMICONDUCTOR DEVICE, ELECTRONIC DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR, DISPOSITIF ÉLECTRONIQUE ET PROCÉDÉ DE FABRICATION DE DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置、電子機器及び半導体装置の製造方法
Abstract:
(EN) [Problem] To provide a semiconductor device, electronic device, and method for manufacturing a semiconductor device in which the effect due to RTN is reduced regardless of the shape of a gate electrode. [Solution] A semiconductor device provided with: a substrate having an element region, which includes a source region and a drain region and in which a channel region is present between the source region and the drain region, and element separation regions provided at least on two sides with respect to a direction orthogonal to the direction in which the source region, channel region, and drain region are arranged; a gate insulation film provided at least on the element region of the substrate from one side to the other side of the element separation regions; and a gate electrode provided on the gate insulation film. The gate insulation film includes an impurity. The impurity concentration in boundary regions, which include the boundaries between the element region and the element separation regions, differs from the impurity concentration in the center region of the gate insulation film.
(FR) Le problème décrit par la présente invention est d'obtenir un dispositif à semi-conducteur, un dispositif électronique et un procédé de fabrication d'un dispositif à semi-conducteur permettant de réduire l'effet causé par un RTN indépendamment de la forme d'une électrode grille. La solution selon l'invention porte sur un dispositif à semi-conducteur comprenant : un substrat présentant une région d'élément, qui comporte une zone de source et une zone de drain, une zone de canal étant ménagée entre la zone de source et la zone de drain, et des régions de séparation d'élément placées au moins sur deux côtés par rapport à une direction orthogonale à la direction dans laquelle la zone de source, la zone de canal, et la zone de drain sont disposées; un film d'isolation de grille placé au moins sur la région d'élément du substrat d'un côté à l'autre côté des régions de séparation d'élément; et une électrode de grille placée sur le film d'isolation de grille. Le film d'isolation de grille contient une impureté. La concentration en impuretés dans les régions de délimitation, qui comprennent les délimitations entre la région d'élément et les régions de séparation d'élément, diffère de la concentration en impuretés dans la région centrale du film d'isolation de grille.
(JA) 【課題】ゲート電極の形状にとらわれることなく、RTNによる影響を低減させる半導体装置、電子機器及び半導体装置の製造方法を提供する。 【解決手段】ソース領域及びドレイン領域を含み、前記ソース領域及び前記ドレイン領域の間にチャネル領域が存在する素子領域と、前記ソース領域、前記チャネル領域及び前記ドレイン領域が配列する方向と直交する方向の両側に少なくとも設けられた素子分離領域を有する基板と、前記素子分離領域の一側から他側に亘って前記基板の前記素子領域上に少なくとも設けられたゲート絶縁膜と、前記ゲート絶縁膜の上に設けられたゲート電極と、を備え、前記ゲート絶縁膜は、不純物を含み、前記素子領域及び前記素子分離領域の境界上を含む境界領域の前記不純物濃度は、前記ゲート絶縁膜の中央領域の前記不純物濃度と異なる、半導体装置
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)