Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019044173) SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND MANUFACTURING METHOD FOR SAME
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/044173 International Application No.: PCT/JP2018/025731
Publication Date: 07.03.2019 International Filing Date: 06.07.2018
IPC:
H01L 33/22 (2010.01) ,H01L 21/205 (2006.01) ,H01L 33/12 (2010.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
20
with a particular shape, e.g. curved or truncated substrate
22
Roughened surfaces, e.g. at the interface between epitaxial layers
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
20
Deposition of semiconductor materials on a substrate, e.g. epitaxial growth
205
using reduction or decomposition of a gaseous compound yielding a solid condensate, i.e. chemical deposition
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
33
Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
02
characterised by the semiconductor bodies
12
with a stress relaxation structure, e.g. buffer layer
Applicants:
東芝マテリアル株式会社 TOSHIBA MATERIALS CO., LTD. [JP/JP]; 神奈川県横浜市磯子区新杉田町8番地 8, Shinsugita-cho, Isogo-ku, Yokohama-shi, Kanagawa 2350032, JP
学校法人 名城大学 MEIJO UNIVERSITY [JP/JP]; 愛知県名古屋市天白区塩釜口一丁目501番地 1-501 Shiogamaguchi, Tempaku-ku, Nagoya-shi, Aichi 4688502, JP
Inventors:
平松 亮介 HIRAMATSU, Ryosuke; JP
佐々木 敦也 SASAKI, Atsuya; JP
平林 英明 HIRABAYASHI, Hideaki; JP
上山 智 KAMIYAMA, Satoshi; JP
Agent:
日向寺 雅彦 HYUGAJI, Masahiko; JP
小崎 純一 KOZAKI, Junichi; JP
市川 浩 ICHIKAWA, Hiroshi; JP
Priority Data:
2017-16713131.08.2017JP
Title (EN) SEMICONDUCTOR LIGHT-EMITTING ELEMENT AND MANUFACTURING METHOD FOR SAME
(FR) ÉLÉMENT ÉLECTROLUMINESCENT À SEMI-CONDUCTEUR ET SON PROCÉDÉ DE FABRICATION
(JA) 半導体発光素子およびその製造方法
Abstract:
(EN) A semiconductor light-emitting element according to one embodiment has a light emission peak wavelength of 380nm to 425nm. The semiconductor light-emitting element has a layered structure which includes a reflective layer, a substrate provided on the reflective layer, and a semiconductor layer provided on the substrate. A surface of the substrate on the semiconductor layer side has a relief structure. The semiconductor layer has a buffer layer made of aluminum nitride with a thickness of 10 nm to 100 nm. The buffer layer is characterized by containing oxygen and satisfying 0.01 ≤ O8nm/O3nm ≤ 0.5 where O3nm (at%) is the oxygen concentration at a depth of 3 nm in the buffer layer and O8nm (at%) is the oxygen concentration at a depth of 8 nm.
(FR) Un élément électroluminescent à semi-conducteur selon un mode de réalisation de la présente invention a une longueur d'onde de crête d'émission de lumière de 380 nm à 425 nm. L'élément électroluminescent à semi-conducteur a une structure stratifiée qui comprend une couche réfléchissante, un substrat disposé sur la couche réfléchissante, et une couche semi-conductrice disposée sur le substrat. Une surface du substrat sur le côté de la couche semi-conductrice a une structure en relief. La couche semi-conductrice comporte une couche tampon en nitrure d'aluminium d'une épaisseur de 10 nm à 100 nm. La couche tampon est caractérisée en ce qu'elle contient de l'oxygène et satisfait 0,01 ≤ O8nm/O3nm ≤ 0,5 où O3nm (at%) est la concentration en oxygène à une profondeur de 3 nm dans la couche tampon et O8nm (at%) est la concentration en oxygène à une profondeur de 8 nm.
(JA) 実施形態に係る半導体発光素子は、発光ピーク波長が380nm以上425nm以下である。前記半導体発光素子は、反射層と、前記反射層の上に設けられた基板と、前記基板の上に設けられた半導体層と、を含む積層構造を具備する。前記基板の前記半導体層側の表面には、凹凸構造が設けられる。前記半導体層は、厚さ10nm以上100nm以下の窒化アルミニウムからなるバッファ層を有する。前記バッファ層は酸素を含有し、前記バッファ層の深さ3nmにおける酸素濃度をO3nm(at%)とし、深さ8nmにおける酸素濃度をO8nm(at%)としたとき、0.01≦O8nm/O3nm≦0.5であることを特徴とする。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)