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1. (WO2019043918) FIELD-EFFECT TRANSISTOR
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Pub. No.: WO/2019/043918 International Application No.: PCT/JP2017/031625
Publication Date: 07.03.2019 International Filing Date: 01.09.2017
IPC:
H01L 21/336 (2006.01) ,H01L 21/338 (2006.01) ,H01L 29/78 (2006.01) ,H01L 29/812 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
338
with a Schottky gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
80
with field effect produced by a PN or other rectifying junction gate
812
with a Schottky gate
Applicants:
三菱電機株式会社 MITSUBISHI ELECTRIC CORPORATION [JP/JP]; 東京都千代田区丸の内二丁目7番3号 7-3, Marunouchi 2-chome, Chiyoda-ku, Tokyo 1008310, JP
Inventors:
渡辺 伸介 WATANABE, Shinsuke; JP
Agent:
高田 守 TAKADA, Mamoru; JP
高橋 英樹 TAKAHASHI, Hideki; JP
Priority Data:
Title (EN) FIELD-EFFECT TRANSISTOR
(FR) TRANSISTOR À EFFET DE CHAMP
(JA) 電界効果トランジスタ
Abstract:
(EN) The field-effect transistor according to the present invention is provided with: a semiconductor substrate; a plurality of drain electrodes provided on a first surface of the semiconductor substrate, the drain electrodes extending in a first direction; a plurality of source electrodes arranged alternately with respect to the plurality of drain electrodes; a plurality of gate electrodes, each of which is provided between the plurality of source electrodes and the plurality of drain electrodes; an input terminal connected to the plurality of gate electrodes; an output terminal connected to the plurality of drain electrodes; and a plurality of metal layers provided to the semiconductor substrate so as to be set apart from the first surface, the metal layers extending in a second direction intersecting the first direction. The plurality of metal layers include a first metal layer, and a second metal layer that is longer than the first metal layer and intersects more drain electrodes than does the first metal layer when viewed from a direction perpendicular to the first surface. From among the plurality of drain electrodes, drain electrodes having a greater line length from the input terminal to the output terminal have more metal layers provided immediately below the drain electrodes.
(FR) La présente invention concerne un transistor à effet de champ comprenant : un substrat semi-conducteur ; une pluralité d'électrodes drain disposées sur une première surface du substrat semi-conducteur et s'étendant dans une première direction ; une pluralité d'électrodes source disposées en alternance relativement à la pluralité d'électrodes drain ; une pluralité d'électrodes grille disposées chacune entre la pluralité d'électrodes source et la pluralité d'électrodes drain ; une borne d'entrée reliée à la pluralité d'électrodes grille ; une borne de sortie reliée à la pluralité d'électrodes drain ; et une pluralité de couches métalliques disposées sur le substrat semi-conducteur de façon à être espacées de la première surface, les couches métalliques s'étendant dans une seconde direction croisant la première direction. La pluralité de couches métalliques comprennent une première couche métallique, et une seconde couche métallique qui est plus longue que la première couche métallique et qui croise plus d'électrodes drain que la première couche métallique vues depuis une direction perpendiculaire à la première surface. Certaines électrodes drain de la pluralité d'électrodes drain dont la longueur de ligne de la borne d'entrée à la borne de sortie est supérieure présentent davantage de couches métalliques disposées directement sous les électrodes drain.
(JA) 本願の発明に係る電界効果トランジスタは、半導体基板と、半導体基板の第1面に設けられ、第1方向に伸びる複数のドレイン電極と、複数のドレイン電極と互いに交互に並ぶ複数のソース電極と、複数のソース電極と複数のドレイン電極との間にそれぞれ設けられた複数のゲート電極と、複数のゲート電極と接続された入力端子と、複数のドレイン電極と接続された出力端子と、半導体基板に第1面と離れて設けられ、第1方向と交差する第2方向に伸びる複数の金属層と、を備え、複数の金属層は、第1金属層と、第1金属層よりも長く、第1面と垂直な方向から見て第1金属層よりも多くのドレイン電極と交差する第2金属層と、を含み、複数のドレイン電極のうち入力端子から出力端子までの線路長が短いドレイン電極ほど、直下に多くの金属層が設けられる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)