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1. (WO2019043888) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
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Pub. No.: WO/2019/043888 International Application No.: PCT/JP2017/031449
Publication Date: 07.03.2019 International Filing Date: 31.08.2017
IPC:
H01L 21/822 (2006.01) ,H01L 21/336 (2006.01) ,H01L 21/8238 (2006.01) ,H01L 27/04 (2006.01) ,H01L 27/092 (2006.01) ,H01L 29/78 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8232
Field-effect technology
8234
MIS technology
8238
Complementary field-effect transistors, e.g. CMOS
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
08
including only semiconductor components of a single kind
085
including field-effect components only
088
the components being field-effect transistors with insulated gate
092
complementary MIS field-effect transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
Applicants:
株式会社ソシオネクスト SOCIONEXT INC. [JP/JP]; 神奈川県横浜市港北区新横浜二丁目10番23 2-10-23 Shin-Yokohama, Kohoku-Ku, Yokohama-shi, Kanagawa 2220033, JP
Inventors:
伊藤 千夏 ITO Chika; --
祖父江 功弥 SOBUE Isaya; --
田中 英俊 TANAKA Hidetoshi; --
Agent:
特許業務法人前田特許事務所 MAEDA & PARTNERS; 大阪府大阪市北区堂島浜1丁目2番1号 新ダイビル23階 Shin-Daibiru Bldg. 23F, 2-1, Dojimahama 1-chome, Kita-ku, Osaka-shi, Osaka 5300004, JP
Priority Data:
Title (EN) SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
(FR) DISPOSITIF DE CIRCUIT INTÉGRÉ À SEMI-CONDUCTEUR
(JA) 半導体集積回路装置
Abstract:
(EN) An ESD protection circuit (101) is provided with: a first fin structure (11) that includes first conductive fins (16); and a second fin structure (12) that includes second conductive fins (17) and faces the first fin structure (11). A first power supply wire (81) connected to the first fin structure (11) and a signal wire (82) connected to the second fin structure (12) are formed in a first wiring layer (M1). A second power supply wire (6) connected to the first power supply wire (81) is formed in a second wiring layer (M2). The width of the second fin structure (12) is larger than that of the first fin structure (11), and the width of the signal wire (82) is larger than that of the first power supply wire (81).
(FR) La présente invention concerne un circuit de protection contre les DES (101) pourvu : d'une première structure à ailettes (11) qui comprend des premières ailettes conductrices (16) ; et d'une seconde structure à ailettes (12) qui comprend des secondes ailettes conductrices (17) et qui fait face à la première structure à ailettes (11). Un premier fil d'alimentation électrique (81) connecté à la première structure à ailettes (11) et un fil de signal (82) connecté à la seconde structure à ailettes (12) sont formés dans une première couche de câblage (M1). Un second fil d'alimentation électrique (6) connecté au premier fil d'alimentation électrique (81) est formé dans une seconde couche de câblage (M2). La largeur de la seconde structure à ailettes (12) est supérieure à celle de la première structure à ailettes (11), et la largeur du fil de signal (82) est supérieure à celle du premier fil d'alimentation électrique (81).
(JA) ESD保護回路(101)は、第1導電型フィン(16)を含む第1フィン構造部(11)と、第2導電型フィン(17)を含み、第1フィン構造部(11)と対向する第2フィン構造部(12)を備える。第1配線層(M1)に、第1フィン構造部(11)と接続された第1電源配線(81)と、第2フィン構造部(12)と接続された信号配線(82)が形成され、第2配線層(M2)に、第1電源配線(81)と接続された第2電源配線(6)が形成される。第2フィン構造部(12)が占める幅は、第1フィン構造部(11)よりも大きく、信号配線(82)の幅は、第1電源配線(81)よりも大きい。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)