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1. WO2019043867 - SEMICONDUCTOR DEVICE

Publication Number WO/2019/043867
Publication Date 07.03.2019
International Application No. PCT/JP2017/031350
International Filing Date 31.08.2017
IPC
H01L 21/822 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78with subsequent division of the substrate into plural individual devices
82to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822the substrate being a semiconductor, using silicon technology
H01L 27/04 2006.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
CPC
H01L 23/58
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for ; , e.g. in combination with batteries
H01L 23/585
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23Details of semiconductor or other solid state devices
58Structural electrical arrangements for semiconductor devices not otherwise provided for ; , e.g. in combination with batteries
585comprising conductive layers or plates or strips or rods or rings
H01L 29/0615
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
0607for preventing surface leakage or controlling electric field concentration
0611for increasing or controlling the breakdown voltage of reverse biased devices
0615by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
H01L 29/0623
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
0607for preventing surface leakage or controlling electric field concentration
0611for increasing or controlling the breakdown voltage of reverse biased devices
0615by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
0619with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
0623Buried supplementary region, e.g. buried guard ring
H01L 29/0626
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
0607for preventing surface leakage or controlling electric field concentration
0611for increasing or controlling the breakdown voltage of reverse biased devices
0615by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
0626with a localised breakdown region, e.g. built-in avalanching region
H01L 29/0638
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; ; Multistep manufacturing processes therefor
02Semiconductor bodies ; ; Multistep manufacturing processes therefor
06characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; ; characterised by the concentration or distribution of impurities within semiconductor regions
0603characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
0607for preventing surface leakage or controlling electric field concentration
0638for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
Applicants
  • 新電元工業株式会社 SHINDENGEN ELECTRIC MANUFACTURING CO., LTD. [JP]/[JP]
Inventors
  • 中村 秀幸 NAKAMURA, Hideyuki
  • 松崎 欣史 MATSUZAKI, Yoshifumi
  • 伊藤 広和 ITO, Hirokazu
Agents
  • 松尾 誠剛 MATSUO, Nobutaka
Priority Data
Publication Language Japanese (JA)
Filing Language Japanese (JA)
Designated States
Title
(EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract
(EN)
A semiconductor device 100 is provided with: an n-type semiconductor substrate 110; a p-type first semiconductor region 120; a p-type surface semiconductor region 130, which has a plurality of second corner sections 131 and a plurality of second side sections 132, said second corner sections and second side sections being formed surrounding the first semiconductor region 120 in a plan view, and which has an impurity concentration that is lower than that of the first semiconductor region 120; and a field plate 154, which has a plurality of field plate corner sections 155 and a plurality of field plate side sections 156, said field plate corner sections and field plate side sections being formed, via an insulating film 140, in a region overlapping the surface semiconductor region 130 in a plan view. The semiconductor device meets either (1) the condition where at least a part thereof meets L1>L2 or (2) the condition where at least a part thereof meets FP1>FP2, and the withstand voltage of the second side sections 132 is lower than that of the second corner sections 131. With this semiconductor device, size can be reduced compared with semiconductor devices having guard ring structures, and compared with conventional semiconductor devices, breakdown strength can be improved as a whole device.
(FR)
L'invention porte sur un dispositif à semi-conducteur 100 comprenant : un substrat semi-conducteur du type n 110 ; une première zone semi-conductrice du type p 120 ; une zone semi-conductrice de surface du type p 130, qui comporte une pluralité de secondes sections de coin 131 et une pluralité de secondes sections de coté 132, lesdites secondes sections de coin et secondes sections de côté étant formées entourant la première zone semi-conductrice 120 en vue plane, et qui possède une concentration d'impuretés qui est inférieure à celle de la première zone semi-conductrice 120 ; et une plaque de champ 154, qui comporte une pluralité de sections de coin de plaque de champ 155 et une pluralité de sections de côté de plaque de champ 156, lesdites sections de coin de plaque de champ et sections de côté de plaque de champ étant formées, avec un film isolant 140 intercalé, dans une zone chevauchant la zone semi-conductrice de surface 130 en vue plane. Le dispositif à semi-conducteur satisfait soit (1) la condition selon laquelle au moins une partie de celui-ci satisfait L1 > L2, soit (2) la condition selon laquelle au moins une partie de celui-ci satisfait FP1 > FP2, et la tension de tenue des secondes sections de côté 132 est inférieure à celle des secondes sections de coin 131. Avec ce dispositif à semi-conducteur, la taille peut être réduite par comparaison avec des dispositifs à semi-conducteur ayant des structures d'anneau de garde, et par comparaison avec des dispositifs à semi-conducteur classiques, la résistance au claquage peut être améliorée pour le dispositif dans son ensemble.
(JA)
n型の半導体基体110と、p型の第1半導体領域120と、平面的に見て第1半導体領域120を囲むように形成された複数の第2コーナー部131及び複数の第2辺部132を有し、第1半導体領域120より不純物濃度が低いp型の表面半導体領域130と、平面的に見て表面半導体領域130と重なる領域に絶縁膜140を介して形成された、複数のフィールドプレートコーナー部155及び複数のフィールドプレート辺部156を有するフィールドプレート154とを備え、(1)少なくとも一部でL1>L2である、及び、(2)少なくとも一部でFP1>FP2である、のうちいずれかの条件を満たし、第2辺部132の耐圧が第2コーナー部131の耐圧よりも低い半導体装置100。 本発明の半導体装置によれば、ガードリング構造の半導体装置よりも小型化することができ、かつ、従来の半導体装置よりも装置全体としての破壊耐量を高くすることができる。
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