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1. (WO2019043867) SEMICONDUCTOR DEVICE
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Pub. No.: WO/2019/043867 International Application No.: PCT/JP2017/031350
Publication Date: 07.03.2019 International Filing Date: 31.08.2017
IPC:
H01L 21/822 (2006.01) ,H01L 27/04 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
Applicants:
新電元工業株式会社 SHINDENGEN ELECTRIC MANUFACTURING CO., LTD. [JP/JP]; 東京都千代田区大手町二丁目2番1号 2-1, Ohtemachi 2-chome, Chiyoda-ku, Tokyo 1000004, JP
Inventors:
中村 秀幸 NAKAMURA, Hideyuki; JP
松崎 欣史 MATSUZAKI, Yoshifumi; JP
伊藤 広和 ITO, Hirokazu; JP
Agent:
松尾 誠剛 MATSUO, Nobutaka; JP
Priority Data:
Title (EN) SEMICONDUCTOR DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR
(JA) 半導体装置
Abstract:
(EN) A semiconductor device 100 is provided with: an n-type semiconductor substrate 110; a p-type first semiconductor region 120; a p-type surface semiconductor region 130, which has a plurality of second corner sections 131 and a plurality of second side sections 132, said second corner sections and second side sections being formed surrounding the first semiconductor region 120 in a plan view, and which has an impurity concentration that is lower than that of the first semiconductor region 120; and a field plate 154, which has a plurality of field plate corner sections 155 and a plurality of field plate side sections 156, said field plate corner sections and field plate side sections being formed, via an insulating film 140, in a region overlapping the surface semiconductor region 130 in a plan view. The semiconductor device meets either (1) the condition where at least a part thereof meets L1>L2 or (2) the condition where at least a part thereof meets FP1>FP2, and the withstand voltage of the second side sections 132 is lower than that of the second corner sections 131. With this semiconductor device, size can be reduced compared with semiconductor devices having guard ring structures, and compared with conventional semiconductor devices, breakdown strength can be improved as a whole device.
(FR) L'invention porte sur un dispositif à semi-conducteur 100 comprenant : un substrat semi-conducteur du type n 110 ; une première zone semi-conductrice du type p 120 ; une zone semi-conductrice de surface du type p 130, qui comporte une pluralité de secondes sections de coin 131 et une pluralité de secondes sections de coté 132, lesdites secondes sections de coin et secondes sections de côté étant formées entourant la première zone semi-conductrice 120 en vue plane, et qui possède une concentration d'impuretés qui est inférieure à celle de la première zone semi-conductrice 120 ; et une plaque de champ 154, qui comporte une pluralité de sections de coin de plaque de champ 155 et une pluralité de sections de côté de plaque de champ 156, lesdites sections de coin de plaque de champ et sections de côté de plaque de champ étant formées, avec un film isolant 140 intercalé, dans une zone chevauchant la zone semi-conductrice de surface 130 en vue plane. Le dispositif à semi-conducteur satisfait soit (1) la condition selon laquelle au moins une partie de celui-ci satisfait L1 > L2, soit (2) la condition selon laquelle au moins une partie de celui-ci satisfait FP1 > FP2, et la tension de tenue des secondes sections de côté 132 est inférieure à celle des secondes sections de coin 131. Avec ce dispositif à semi-conducteur, la taille peut être réduite par comparaison avec des dispositifs à semi-conducteur ayant des structures d'anneau de garde, et par comparaison avec des dispositifs à semi-conducteur classiques, la résistance au claquage peut être améliorée pour le dispositif dans son ensemble.
(JA) n型の半導体基体110と、p型の第1半導体領域120と、平面的に見て第1半導体領域120を囲むように形成された複数の第2コーナー部131及び複数の第2辺部132を有し、第1半導体領域120より不純物濃度が低いp型の表面半導体領域130と、平面的に見て表面半導体領域130と重なる領域に絶縁膜140を介して形成された、複数のフィールドプレートコーナー部155及び複数のフィールドプレート辺部156を有するフィールドプレート154とを備え、(1)少なくとも一部でL1>L2である、及び、(2)少なくとも一部でFP1>FP2である、のうちいずれかの条件を満たし、第2辺部132の耐圧が第2コーナー部131の耐圧よりも低い半導体装置100。 本発明の半導体装置によれば、ガードリング構造の半導体装置よりも小型化することができ、かつ、従来の半導体装置よりも装置全体としての破壊耐量を高くすることができる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)