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1. WO2019043710 - SYSTEM AND METHOD FOR HIGH THROUGHPUT IN MULTIPLE COMPUTATIONS

Publication Number WO/2019/043710
Publication Date 07.03.2019
International Application No. PCT/IL2018/050965
International Filing Date 30.08.2018
IPC
G06F 12/08 2016.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
G06F 12/0802
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
G06F 13/14 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
G06F 9/50 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
46Multiprogramming arrangements
50Allocation of resources, e.g. of the central processing unit
G06T 1/20 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
1General purpose image data processing
20Processor architectures; Processor configuration, e.g. pipelining
G06T 1/60 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
1General purpose image data processing
60Memory management
CPC
G06F 12/0806
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
12Accessing, addressing or allocating within memory systems or architectures
02Addressing or allocation; Relocation
08in hierarchically structured memory systems, e.g. virtual memory systems
0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
0806Multiuser, multiprocessor or multiprocessing cache systems
G06F 13/14
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
G06F 13/30
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
14Handling requests for interconnection or transfer
20for access to input/output bus
28using burst mode transfer, e.g. direct memory access ; DMA; , cycle steal
30with priority control
G06F 13/4022
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
13Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
38Information transfer, e.g. on bus
40Bus structure
4004Coupling between buses
4022using switching circuits, e.g. switching matrix, connection or expansion network
G06F 2212/621
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
2212Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
62Details of cache specific to multiprocessor cache arrangements
621Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
G06F 9/3851
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
3851from multiple instruction streams, e.g. multistreaming
Applicants
  • RAIL VISION LTD [IL]/[IL]
Inventors
  • HANIA, Shahar
  • ZELTZER, Hanan
Agents
  • BARKAI, Yosi
Priority Data
62/552,47531.08.2017US
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) SYSTEM AND METHOD FOR HIGH THROUGHPUT IN MULTIPLE COMPUTATIONS
(FR) SYSTÈME ET PROCÉDÉ D'AMÉLIORATION DU DÉBIT DANS DE NOMBREUX CALCULS
Abstract
(EN)
Device, circuit and method are configured to enhance throughout of processing of vast amount of data such as video stream. In some embodiment frequently used data blocks are stored in a fast RAM of the processor. In another embodiment received stream of data is divided to plurality of data portions and is streamed concurrently to streaming multiprocessors of a graphic processing unit (GPU) and is processed concurrently before the entire stream is loaded.
(FR)
L'invention concerne un dispositif, un circuit, et un procédé configurés pour améliorer le débit de traitement d'une grande quantité de données telles qu'un flux vidéo. Dans un mode de réalisation, des blocs de données fréquemment utilisés sont stockés dans une RAM rapide du processeur. Dans un autre mode de réalisation, le flux de données reçu est divisé en une pluralité de portions de données, il est diffusé en continu simultanément à des multiprocesseurs de diffusion en continu d'une unité de traitement graphique (GPU), et il est traité simultanément avant que le flux entier soit chargé.
Also published as
JP2020512508
Latest bibliographic data on file with the International Bureau