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1. (WO2019043510) SEMICONDUCTOR DEVICE AND DISPLAY DEVICE
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Pub. No.: WO/2019/043510 International Application No.: PCT/IB2018/056333
Publication Date: 07.03.2019 International Filing Date: 22.08.2018
IPC:
H01L 29/786 (2006.01) ,G02F 1/1333 (2006.01) ,G02F 1/1345 (2006.01) ,G02F 1/1368 (2006.01) ,G09F 9/30 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
1333
Constructional arrangements
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
1333
Constructional arrangements
1345
Conductors connecting electrodes to cell terminals
G PHYSICS
02
OPTICS
F
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH IS MODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THE DEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY, COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g. SWITCHING, GATING, MODULATING OR DEMODULATING; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF; FREQUENCY-CHANGING; NON-LINEAR OPTICS; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
1
Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
01
for the control of the intensity, phase, polarisation or colour
13
based on liquid crystals, e.g. single liquid crystal display cells
133
Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
136
Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
1362
Active matrix addressed cells
1368
in which the switching element is a three-electrode device
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
F
DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
9
Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
30
in which the desired character or characters are formed by combining individual elements
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
株式会社半導体エネルギー研究所 SEMICONDUCTOR ENERGY LABORATORY CO., LTD. [JP/JP]; 神奈川県厚木市長谷398 398, Hase, Atsugi-shi, Kanagawa 2430036, JP
Inventors:
島行徳 SHIMA, Yukinori; --
中田昌孝 NAKADA, Masataka; --
土橋正佳 DOBASHI, Masayoshi; --
岡崎健一 OKAZAKI, Kenichi; JP
Priority Data:
2017-16824401.09.2017JP
Title (EN) SEMICONDUCTOR DEVICE AND DISPLAY DEVICE
(FR) DISPOSITIF À SEMI-CONDUCTEUR ET DISPOSITIF D'AFFICHAGE
(JA) 半導体装置、及び表示装置
Abstract:
(EN) Provided is a semiconductor device that can achieve high integration. The semiconductor device has a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a first conductive layer, and a second conductive layer. The second semiconductor layer is located above the first semiconductor layer. The second conductive layer is located above the second semiconductor layer. The second insulating layer is provided to cover an upper surface and a side surface of the second conductive layer. The second conductive layer and the second insulating layer have a first opening. The third semiconductor layer is provided where an upper surface of the second insulating layer, a side surface of the first opening, and the second semiconductor layer touch. The first insulating layer is located between the first conductive layer and the third semiconductor layer. The third insulating layer is located between the first insulating layer and the first conductive layer. The fourth insulating layer is provided to surround the first conductive layer.
(FR) L'invention concerne un dispositif à semi-conducteur qui permet de réaliser une haute intégration. Le dispositif à semi-conducteur comprend une première couche semi-conductrice, une seconde couche semi-conductrice, une troisième couche semi-conductrice, une première couche isolante, une seconde couche isolante, une troisième couche isolante, une quatrième couche isolante, une première couche conductrice et une seconde couche conductrice. La seconde couche semi-conductrice est située au-dessus de la première couche semi-conductrice. La seconde couche conductrice est située au-dessus de la seconde couche semi-conductrice. La seconde couche isolante est disposée de façon à recouvrir une surface supérieure et une surface latérale de la seconde couche conductrice. La seconde couche conductrice et la seconde couche isolante ont une première ouverture. La troisième couche semi-conductrice est disposée à l'endroit où une surface supérieure de la seconde couche isolante, une surface latérale de la première ouverture et la seconde couche semi-conductrice se touchent. La première couche isolante est située entre la première couche conductrice et la troisième couche semi-conductrice. La troisième couche isolante est située entre la première couche isolante et la première couche conductrice. La quatrième couche isolante est prévue pour entourer la première couche conductrice.
(JA) 要約書 高集積化が可能な半導体装置を提供する。 半導体装置は、第1の半導体層、第2の半導体層、第3の半導体層、第1の絶縁層、第2の絶縁層、第3の 絶縁層、第4の絶縁層、第1の導電層、及び第2の導電層を有する。第2の半導体層は、第1の半導体層上 に位置し、第2の導電層は、第2の半導体層上に位置し、第2の絶縁層は、第2の導電層の上面と側面とを 覆うように設けられる。第2の導電層と、第2の絶縁層とは、第1の開口を有し、第3の半導体層は、第2の 絶縁層の上面と、第1の開口の側面と、第2の半導体層とが接する位置に設けられる。第1の絶縁層は、第 1の導電層と、第3の半導体層との間に位置し、第3の絶縁層は、第1の絶縁層と、第1の導電層との間に 位置し、第4の絶縁層は、第1の導電層を囲うように設けられる。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Japanese (JA)
Filing Language: Japanese (JA)