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1. (WO2019043478) PROTECTION OF LOW TEMPERATURE ISOLATION FILL
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Pub. No.: WO/2019/043478 International Application No.: PCT/IB2018/055863
Publication Date: 07.03.2019 International Filing Date: 03.08.2018
IPC:
H01L 29/06 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
Applicants:
INTERNATIONAL BUSINESS MACHINES CORPORATION [US/US]; New Orchard Road Armonk, New York 10504, US
IBM UNITED KINGDOM LIMITED [GB/GB]; PO Box 41, North Harbour Portsmouth Hampshire PO6 3AU, GB (MG)
IBM (CHINA) INVESTMENT COMPANY LIMITED [CN/CN]; 25/F, Pangu Plaza No.27, Central North 4th Ring Road, Chaoyang District, Beijing 100101, CN (MG)
Inventors:
STRANE, Jay, William; US
SADANA, Devendra; US
BELYANSKY, Michael; US
GUO, Dechao; US
CONTI, Richard; US
Agent:
WILLIAMS, Julian; GB
Priority Data:
15/688,15428.08.2017US
Title (EN) PROTECTION OF LOW TEMPERATURE ISOLATION FILL
(FR) PROTECTION DE REMPLISSAGE D'ISOLATION À BASSE TEMPÉRATURE
Abstract:
(EN) A semiconductor structure includes a plurality of semiconductor fins on an upper surface of a semiconductor substrate. The semiconductor fins spaced apart from one another by a respective trench to define a fin pitch. A multi-layer electrical isolation region is contained in each trench. The multi-layer electrical isolation region includes an oxide layer and a protective layer. The oxide layer includes a first material on an upper surface of the semiconductor substrate. The protective layer includes a second material on an upper surface of the oxide layer. The second material is different than the first material. The first material has a first etch resistance and the second material has a second etch resistance that is greater than the first etch resistance.
(FR) L'invention concerne une structure semi-conductrice comprenant une pluralité d'ailettes semi-conductrices sur une surface supérieure d'un substrat semi-conducteur. Les ailettes semi-conductrices sont espacées les unes des autres par une tranchée respective pour définir un pas d'ailette. Une région d'isolation électrique multicouche est contenue dans chaque tranchée. La région d'isolation électrique multicouche comprend une couche d'oxyde et une couche de protection. La couche d'oxyde comprend un premier matériau sur une surface supérieure du substrat semi-conducteur. La couche de protection comprend un second matériau sur une surface supérieure de la couche d'oxyde. Le second matériau est différent du premier matériau. Le premier matériau présente une première résistance à la gravure et le second matériau présente une seconde résistance à la gravure qui est plus grande que la première résistance à la gravure.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)