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1. (WO2019042429) INTEGRATED CIRCUIT CHIP AND MANUFACTURING METHOD THEREFOR, AND GATE DRIVE CIRCUIT
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Pub. No.: WO/2019/042429 International Application No.: PCT/CN2018/103620
Publication Date: 07.03.2019 International Filing Date: 31.08.2018
IPC:
H01L 29/739 (2006.01) ,H01L 29/78 (2006.01) ,H01L 21/8249 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
70
Bipolar devices
72
Transistor-type devices, i.e. able to continuously respond to applied control signals
739
controlled by field effect
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
822
the substrate being a semiconductor, using silicon technology
8248
Combination of bipolar and field-effect technology
8249
Bipolar and MOS technology
Applicants:
无锡华润上华科技有限公司 CSMC TECHNOLOGIES FAB2 CO., LTD. [CN/CN]; 中国江苏省无锡市 新区新洲路8号 No.8 Xinzhou Road Wuxi New District, Jiangsu 214028, CN
Inventors:
顾力晖 GU, Lihui; CN
张森 ZHANG, Sen; CN
齐从明 QI, Congming; CN
Agent:
广州华进联合专利商标代理有限公司 ADVANCE CHINA IP LAW OFFICE; 中国广东省广州市天河区珠江东路6号4501房 (部位:自编01-03和08-12单元)(仅限办公用途) Room 4501, No. 6 Zhujiang East Road, Tianhe District, Guangzhou Guangdong 510623, CN
Priority Data:
201710779965.901.09.2017CN
Title (EN) INTEGRATED CIRCUIT CHIP AND MANUFACTURING METHOD THEREFOR, AND GATE DRIVE CIRCUIT
(FR) PUCE DE CIRCUIT INTÉGRÉ ET PROCÉDÉ DE FABRICATION ASSOCIÉ, ET CIRCUIT D'ATTAQUE DE GRILLE
(ZH) 集成电路芯片及其制作方法、栅驱动电路
Abstract:
(EN) An integrated circuit chip and a manufacturing method therefor, and a gate drive circuit, the integrated circuit chip comprising: a semiconductor substrate (103), a high voltage island (101a) being formed in the semiconductor substrate (103); a high voltage junction terminal (102a), the high voltage junction terminal (102a) surrounding the high voltage island (101a), a depletion type MOS device (N1) being formed on the high voltage junction terminal (102a), a gate electrode and a drain electrode of the depletion type MOS device (N1) being short connected, and a source electrode of the depletion type MOS device (N1) being connected to a high side power supply end (VB) of the integrated circuit chip; and a bipolar transistor (Q1), a collector electrode of the bipolar transistor (Q1) being short connected to the substrate and being connected to a low side power supply end (VCC) of the integrated circuit chip, an emitter of the bipolar transistor (Q1) being connected to a gate electrode of the depletion type MOS device (N1).
(FR) La présente invention concerne une puce de circuit intégré et son procédé de fabrication, et un circuit d'attaque de grille, la puce de circuit intégré comprenant : un substrat semi-conducteur (103), un îlot haute tension (101a) étant formé dans le substrat semi-conducteur (103) ; une borne de jonction haute tension (102a), la borne de jonction haute tension (102a) entourant l'îlot haute tension (101a), un dispositif MOS de type à appauvrissement (N1) étant formé sur la borne de jonction haute tension (102a), une électrode de grille et une électrode de drain du dispositif MOS de type à appauvrissement (N1) étant court-circuitée, et une électrode de source du dispositif MOS de type à appauvrissement (N1) étant connectée à une extrémité d'alimentation électrique côté haut (VB) de la puce de circuit intégré ; et un transistor bipolaire (Q1), une électrode de collecteur du transistor bipolaire (Q1) étant court-connectée au substrat et étant connectée à une extrémité d'alimentation électrique côté bas (VCC) de la puce de circuit intégré, un émetteur du transistor bipolaire (Q1) étant connecté à une électrode de grille du dispositif MOS de type à appauvrissement (N1).
(ZH) 一种集成电路芯片及其制作方法、栅驱动电路,该集成电路芯片包括:半导体衬底(103),在半导体衬底(103)中形成有高压岛(101a);高压结终端(102a),所述高压结终端(102a)包围所述高压岛(101a),在所述高压结终端(102a)形成有耗尽型MOS器件(N1),所述耗尽型MOS器件(N1)的栅极和漏极短接,所述耗尽型MOS器件(N1)的源极与所述集成电路芯片的高侧电源端(VB)连接;双极晶体管(Q1),所述双极晶体管(Q1)的集电极和基极短接并与所述集成电路芯片的低侧电源端(VCC)连接,所述双极晶体管(Q1)的发射极与所述耗尽型MOS器件(N1)的栅极连接。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)