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1. (WO2019042251) THIN-FILM TRANSISTOR, THIN-FILM TRANSISTOR PREPARATION METHOD, AND ARRAY SUBSTRATE
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Pub. No.: WO/2019/042251 International Application No.: PCT/CN2018/102505
Publication Date: 07.03.2019 International Filing Date: 27.08.2018
IPC:
H01L 29/41 (2006.01) ,H01L 21/336 (2006.01) ,H01L 29/786 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No.10 Jiuxianqiao Rd., Chaoyang District, Beijing 100015, CN
Inventors:
王国英 WANG, Guoying; CN
宋振 SONG, Zhen; CN
孙宏达 SUN, Hongda; CN
Agent:
北京天昊联合知识产权代理有限公司 TEE&HOWE INTELLECTUAL PROPERTY ATTORNEYS; 中国北京市 东城区建国门内大街28号民生金融中心D座10层陈源 Yuan CHEN 10th Floor, Tower D, Minsheng Financial Center, 28 Jianguomennei Avenue, Dongcheng District Beijing 100005, CN
Priority Data:
201710749797.928.08.2017CN
Title (EN) THIN-FILM TRANSISTOR, THIN-FILM TRANSISTOR PREPARATION METHOD, AND ARRAY SUBSTRATE
(FR) TRANSISTOR À COUCHES MINCES, PROCÉDÉ DE FABRICATION DE TRANSISTOR À COUCHES MINCES, ET SUBSTRAT DE MATRICE
(ZH) 薄膜晶体管、薄膜晶体管制备方法和阵列基板
Abstract:
(EN) The present application provides a thin-film transistor, a thin-film transistor preparation method, and an array substrate. The thin-film transistor comprises: a gate, disposed above a substrate and provided with a first side surface and a second side surface that are opposite to each other; and an active layer, sandwiched between the first side surface and the second side surface of the gate and provided with a third side surface and a fourth side surface. The third side surface of the active layer is opposite to and spaced from the first side surface of the gate, the fourth side surface of the active layer is opposite to and spaced from the second side surface of the gate, and at least one part of the gate and at least one part of the active layer are located in a same scope in the height direction.
(FR) La présente invention concerne un transistor à couches minces, un procédé de préparation de transistor à couches minces et un substrat de matrice. Le transistor à couches minces comprend : une gâchette, disposée au-dessus d'un substrat et pourvue d'une première surface latérale et d'une deuxième surface latérale qui sont opposées l'une à l'autre ; et une couche active, prise en sandwich entre la première surface latérale et la deuxième surface latérale de la gâchette et pourvue d'une troisième surface latérale et d'une quatrième surface latérale. La troisième surface latérale de la couche active est opposée à la première surface latérale de la gâchette et espacée de celle-ci, la quatrième surface latérale de la couche active est opposée à la deuxième surface latérale de la gâchette et espacée de celle-ci, et au moins une partie de la gâchette et au moins une partie de la couche active sont situées dans une même portée dans le sens de la hauteur.
(ZH) 本申请提供了一种薄膜晶体管、薄膜晶体管的制备方法和阵列基板。该薄膜晶体管包括:设置在衬底上方的栅极,其具有彼此相对的第一侧表面和第二侧表面;以及有源层,其夹设在所述栅极的第一侧表面和第二侧表面之间,并且具有第三侧表面和第四侧表面。所述有源层的第三侧表面和所述栅极的第一侧表面相对且间隔开,所述有源层的第四侧表面和所述栅极的第二侧表面相对且间隔开,所述栅极的至少一部分与所述有源层的至少一部分在高度方向上处于相同的范围。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)