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1. (WO2019042178) WORD LINE CONTACT STRUCTURE FOR THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATION METHODS THEREOF
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Pub. No.: WO/2019/042178 International Application No.: PCT/CN2018/101308
Publication Date: 07.03.2019 International Filing Date: 20.08.2018
IPC:
H01L 27/11529 (2017.01) ,H01L 27/11551 (2017.01)
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Applicants:
YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN/CN]; Room 7018, No.18, Huaguang Road, Guandong Science and Technology Industrial Park East Lake High-Tech Development Zone Wuhan, Hubei 430074, CN
Inventors:
ZHU, Jifeng; CN
LU, Zhenyu; CN
CHEN, Jun; CN
HU, Si Ping; CN
DAI, Xiaowang; CN
YAO, Lan; CN
XIAO, Li Hong; CN
ZHENG, A Man; CN
BAO, Kun; CN
YANG, Haohao; CN
Agent:
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.; 10th Floor, Tower C, Beijing Global Trade Center 36 North Third Ring Road East, Dongcheng District Beijing 100013, CN
Priority Data:
201710774754.631.08.2017CN
Title (EN) WORD LINE CONTACT STRUCTURE FOR THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATION METHODS THEREOF
(FR) STRUCTURE DE CONTACT DE LIGNE DE MOTS POUR DISPOSITIFS DE MÉMOIRE TRIDIMENSIONNELS ET PROCÉDÉS DE FABRICATION ASSOCIÉS
Abstract:
(EN) Embodiments of semiconductor structures including word line contact structures for three-dimensional memory devices and fabrication methods for forming word line contact structures are disclosed. The semiconductor structures include a staircase structure having a plurality of steps, and each step includes a conductive layer disposed over a dielectric layer. The semiconductor structures further include a barrier layer disposed over a portion of the conductive layer of each step. The semiconductor structures also include an etch-stop layer disposed on the barrier layer and an insulating layer disposed on the etch-stop layer. The semiconductor structures also include a plurality of conductive structures formed in the insulating layer and each conductive structure is formed on the conductive layer of each step.
(FR) L'invention concerne des modes de réalisation de structures semi-conductrices comprenant des structures de contact de ligne de mots pour des dispositifs de mémoire tridimensionnels et des procédés de fabrication pour former des structures de contact de ligne de mots. Les structures semi-conductrices comprennent une structure en escalier ayant une pluralité d'étages, et chaque étage comprend une couche conductrice disposée sur une couche diélectrique. Les structures semi-conductrices comprennent en outre une couche barrière disposée sur une partie de la couche conductrice de chaque étage. Les structures semi-conductrices comprennent également une couche d'arrêt de gravure disposée sur la couche barrière et une couche isolante disposée sur la couche d'arrêt de gravure. Les structures semi-conductrices comprennent également une pluralité de structures conductrices formées dans la couche isolante et chaque structure conductrice est formée sur la couche conductrice de chaque étage.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)