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1. (WO2019042120) CHIP PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE
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Pub. No.: WO/2019/042120 International Application No.: PCT/CN2018/100301
Publication Date: 07.03.2019 International Filing Date: 13.08.2018
IPC:
H01L 25/18 (2006.01) ,H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
25
Assemblies consisting of a plurality of individual semiconductor or other solid state devices
18
the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/-H01L51/160
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
华为技术有限公司 HUAWEI TECHNOLOGIES CO., LTD. [CN/CN]; 中国广东省深圳市 龙岗区坂田华为总部办公楼 Huawei Administration Building Bantian, Longgang District Shenzhen, Guangdong 518129, CN
Inventors:
王双福 WANG, Shuangfu; CN
Agent:
北京中博世达专利商标代理有限公司 BEIJING ZBSD PATENT & TRADEMARK AGENT LTD.; 中国北京市 海淀区交大东路31号11号楼8层 8F, Building 11 No. 31 Jiaoda East Road, Haidian District Beijing 100044, CN
Priority Data:
201710771362.429.08.2017CN
Title (EN) CHIP PACKAGING STRUCTURE AND MANUFACTURING METHOD THEREFOR, AND ELECTRONIC DEVICE
(FR) STRUCTURE D'ENCAPSULATION DE PUCE ET SON PROCÉDÉ DE FABRICATION, ET DISPOSITIF ÉLECTRONIQUE
(ZH) 一种芯片封装结构及其制作方法、电子设备
Abstract:
(EN) Disclosed are a chip packaging structure and a manufacturing method therefor, and an electronic device, which relate to the technical field of electronic packaging and solve the problem of a chip packaging structure being relatively thick. The specific solution involves: the chip packaging structure comprising a main chip; a first rewiring layer, which is arranged on an active face of the main chip and is electrically connected to the main chip; a second rewiring layer, which is arranged on a back face of the main chip and is in contact with the back face of the main chip; a first electrical connection part, which is arranged between the first rewiring layer and the second rewiring layer, wherein the first electrical connection part is used for electrically connecting the first rewiring layer to the second rewiring layer; and overlay chips, which are arranged on one side, away from the main chip, of the second rewiring layer and are electrically connected to the second rewiring layer. The chip packaging structure provided in the present application is used for being connected to a circuit board in an electronic device.
(FR) L'invention se rapporte au domaine technique de l'encapsulation électronique et porte sur une structure d'encapsulation de puce et son procédé de fabrication, et sur un dispositif électronique qui résolvent le problème d'une structure d'encapsulation de puce relativement épaisse. La solution spécifique comprend : la structure d'encapsulation de puce comprenant une puce principale; une première couche de recâblage, qui est disposée sur une face active de la puce principale et électriquement connectée à la puce principale; une seconde couche de recâblage, qui est disposée sur une face arrière de la puce principale et en contact avec cette dernière; une première partie connexion électrique, qui est placée entre la première et la seconde couche de recâblage, la première partie connexion électrique étant destinée à connecter électriquement la première couche de recâblage à la seconde couche de recâblage; et des puces de superposition, qui sont disposées sur un côté de la seconde couche de recâblage, à distance de la puce principale, et qui sont électriquement connectées à la seconde couche de recâblage. La structure d'encapsulation de puce selon la présente invention est destinée à être connectée à une carte de circuit imprimé dans un dispositif électronique.
(ZH) 本申请公开了一种芯片封装结构及其制作方法、电子设备,涉及电子封装技术领域,解决了芯片封装结构厚度较大的问题。具体方案:该芯片封装结构包括:主芯片;第一重布线层,设置于主芯片的主动面,且与主芯片电连接;第二重布线层,设置于主芯片的背面,且与主芯片的背面相接触;第一电连接件,设置于第一重布线层和第二重布线层之间,第一电连接件用于将第一重布线层和第二重布线层电连接;叠加芯片,设置于第二重布线层背离主芯片的一侧,且与第二重布线层电连接。本申请提供的芯片封装结构用于与电子设备中的电路板相连接。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)