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1. (WO2019042107) ARRAY SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE
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Pub. No.: WO/2019/042107 International Application No.: PCT/CN2018/099537
Publication Date: 07.03.2019 International Filing Date: 09.08.2018
IPC:
H01L 23/58 (2006.01) ,H01L 27/12 (2006.01) ,H01L 21/84 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
23
Details of semiconductor or other solid state devices
58
Structural electrical arrangements for semiconductor devices not otherwise provided for
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
78
with subsequent division of the substrate into plural individual devices
82
to produce devices, e.g. integrated circuits, each consisting of a plurality of components
84
the substrate being other than a semiconductor body, e.g. being an insulating body
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
成都京东方光电科技有限公司 CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国四川省成都市 高新区(西区)合作路1188号 No.1188 Hezuo Rd., (West Zone), Hi-tech Development Zone Chengdu, Sichuan 611731, CN
Inventors:
徐元杰 XU, Yuanjie; CN
高山 GAO, Shan; CN
Agent:
中国专利代理(香港)有限公司 CHINA PATENT AGENT (H.K.) LTD.; 中国香港特别行政区 湾仔港湾道23号鹰君中心22号楼 22/F, Great Eagle Centre 23 Harbour Road, Wanchai Hong Kong, CN
Priority Data:
201710778806.731.08.2017CN
Title (EN) ARRAY SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE
(FR) SUBSTRAT DE RÉSEAU, SON PROCÉDÉ DE FABRICATION ET DISPOSITIF D'AFFICHAGE
(ZH) 阵列基板及其制作方法以及显示装置
Abstract:
(EN) The present disclosure relates to the technical field of display, and provides an array substrate, a method for manufacturing same, and a display device. The array substrate comprises a display area and a wiring area surrounding the display area. The array substrate further comprises a base substrate as well as a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, and a patterned shielding layer sequentially arranged on the base substrate. The shielding layer comprises a shielding part located in the wiring area. The first conductive layer comprises a first signal line lead located in the wiring area, the second conductive layer comprises a second signal line lead located in the wiring area, and orthographic projections of the first signal line lead and second signal line lead on the base substrate do not overlap. A difference value between a vertical distance from the first signal line lead to the shielding layer and a vertical distance from the second signal line lead to the shielding layer is smaller than the thickness of the first insulating layer.
(FR) La présente invention se rapporte au champ technique de l’affichage, et concerne un substrat de réseau, son procédé de fabrication et un dispositif d’affichage. Le substrat de réseau comprend une zone d’affichage et une zone de câblage entourant la zone d'affichage. Le substrat de réseau comprend en outre un substrat de base ainsi qu'une première couche conductrice, une première couche isolante, une seconde couche conductrice, une seconde couche isolante, et une couche de blindage à motifs disposée de manière séquentielle sur le substrat de base. La couche de blindage comprend une partie de blindage située dans la zone de câblage. La première couche conductrice comprend un premier conducteur de ligne de signal situé dans la zone de câblage, la seconde couche conductrice comprenant un second conducteur de ligne de signal situé dans la zone de câblage, et des projections orthographiques du premier conducteur de ligne de signal et du second conducteur de ligne de signal sur le substrat de base ne se chevauchent pas. Une valeur de différence entre une distance verticale du premier conducteur de ligne de signal à la couche de blindage et une distance verticale du second conducteur de ligne de signal à la couche de blindage est inférieure à l'épaisseur de la première couche isolante.
(ZH) 本公开涉及显示技术领域,并且提供了阵列基板及其制作方法以及显示装置。阵列基板包括显示区域以及围绕显示区域的走线区域。阵列基板还包括衬底基板以及依次设置在衬底基板上的第一导电层、第一绝缘层、第二导电层、第二绝缘层和图案化的屏蔽层。屏蔽层包括位于走线区域中的屏蔽部分。第一导电层包括位于走线区域中的第一信号线引线,并且第二导电层包括位于走线区域中的第二信号线引线,第一信号线引线与第二信号线引线在衬底基板上的正投影不重叠。第一信号线引线到屏蔽层的垂直距离与第二信号线引线到屏蔽层的垂直距离之间的差值小于第一绝缘层的厚度。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)