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1. (WO2019042098) ARRAY COMMON SOURCE STRUCTURES OF THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF
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Pub. No.: WO/2019/042098 International Application No.: PCT/CN2018/099297
Publication Date: 07.03.2019 International Filing Date: 08.08.2018
IPC:
H01L 27/115 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04
the substrate being a semiconductor body
10
including a plurality of individual components in a repetitive configuration
105
including field-effect components
112
Read-only memory structures
115
Electrically programmable read-only memories
Applicants:
YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN/CN]; Room 7018, No.18, Huaguang Road Guandong Science and Technology Industrial Park East Lake High-Tech Development Zone Wuhan, Hubei 430074, CN
Inventors:
XIAO, Li Hong; CN
LU, Zhenyu; CN
TAO, Qian; CN
YAO, Lan; CN
Agent:
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.; 10th Floor, Tower C, Beijing Global Trade Center 36 North Third Ring Road East, Dongcheng District Beijing 100013, CN
Priority Data:
201710775892.631.08.2017CN
Title (EN) ARRAY COMMON SOURCE STRUCTURES OF THREE-DIMENSIONAL MEMORY DEVICES AND FABRICATING METHODS THEREOF
(FR) STRUCTURES DE SOURCE COMMUNE DE RÉSEAU DE DISPOSITIFS DE MÉMOIRE TRIDIMENSIONNELS ET LEURS PROCÉDÉS DE FABRICATION
Abstract:
(EN) A method for forming a 3D memory device is disclosed. The method comprises: forming an alternating conductive/dielectric stack on a substrate; forming a silt vertically penetrating the alternating conductive/dielectric stack; forming an isolation layer on a sidewall of the silt; forming a first conductive layer covering the isolation layer; performing a plasma treatment followed by a first doping process to the first conductive layer; forming a second conductive layer covering the first conductive and filling the slit; performing a second doping process followed by a rapid thermal crystallization process to the second conductive layer; removing an upper portion of the first conductive layer and the second conductive layer to form a recess in the slit; and forming a third conductive layer in the recess.
(FR) La présente invention concerne un procédé de formation de dispositif mémoire 3D. Le procédé comprend les étapes suivantes consistant : à former un empilement conducteur/diélectrique alterné sur un substrat ; à former une fente pénétrant verticalement dans l'empilement conducteur/diélectrique alterné ; à former une couche d'isolation sur une paroi latérale de la fente ; à former une première couche conductrice recouvrant la couche d'isolation ; à réaliser un traitement au plasma suivi d'un premier processus de dopage sur la première couche conductrice ; à former une deuxième couche conductrice recouvrant la première couche conductrice et remplissant la fente ; à réaliser un second processus de dopage suivi d'un processus de cristallisation thermique rapide sur la deuxième couche conductrice; à retirer une partie supérieure de la première couche conductrice et de la deuxième couche conductrice pour former un évidement dans la fente ; et à former une troisième couche conductrice dans l'évidement.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)