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1. WO2019042091 - STAIRCASE STRUCTURE FOR MEMORY DEVICE

Publication Number WO/2019/042091
Publication Date 07.03.2019
International Application No. PCT/CN2018/098962
International Filing Date 06.08.2018
IPC
H01L 27/11551 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11551characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 27/11578 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
CPC
H01L 21/0273
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
0271comprising organic layers
0273characterised by the treatment of photoresist layers
H01L 21/31144
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02Manufacture or treatment of semiconductor devices or of parts thereof
04the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
18the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
31to form insulating layers thereon, e.g. for masking or by using photolithographic techniques
3105After-treatment
311Etching the insulating layers ; by chemical or physical means
31144using masks
H01L 27/11524
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11521characterised by the memory core region
11524with cell select transistors, e.g. NAND
H01L 27/11529
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11517with floating gate
11526characterised by the peripheral circuit region
11529of memory regions comprising cell select transistors, e.g. NAND
H01L 27/1157
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11568characterised by the memory core region
1157with cell select transistors, e.g. NAND
H01L 27/11575
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11575characterised by the boundary region between the core and peripheral circuit regions
Applicants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • LU, Zhenyu
  • CHEN, Jun
  • DAI, Xiaowang
  • ZHU, Jifeng
  • TAO, Qian
  • HUANG, Yuru
  • HU, Siping
  • YAO, Lan
  • XIAO, Lihong
  • ZHENG, Aman
  • BAO, Kun
  • YANG, Haohao
Agents
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Priority Data
201710750398.428.08.2017CN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) STAIRCASE STRUCTURE FOR MEMORY DEVICE
(FR) STRUCTURE EN ESCALIER POUR DISPOSITIF DE MÉMOIRE
Abstract
(EN)
A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure (800) disposed over a substrate (101). The staircase structure (800) includes a plurality of layer stacks, where each layer stack is made of a first material layer (502) over a portion of a second material layer (840). The staircase structure (800) further includes a plurality of landing pads (820), where each landing pad (820) is disposed over another portion of the second material layer (840) of a respective layer stack.
(FR)
L'invention concerne une structure semi-conductrice. La structure semi-conductrice inclut une structure en escalier (800) dispose au-dessus d'un substrat (101). La structure en escalier (800) inclut une pluralité d'empilements de couches, chaque empilement de couches étant constitué d'une première couche de matériau (502) au-dessus d'une partie d'une deuxième couche de matériau (840). La structure en escalier (800) inclut en outre une pluralité de pastilles de connexion (820), chaque pastille de connexion (820) étant disposée au-dessus d'une autre partie d'une deuxième couche de matériau (840) d'un empilement de couches respectif.
Also published as
Latest bibliographic data on file with the International Bureau