Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019042091) STAIRCASE STRUCTURE FOR MEMORY DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/042091 International Application No.: PCT/CN2018/098962
Publication Date: 07.03.2019 International Filing Date: 06.08.2018
IPC:
H01L 27/11551 (2017.01) ,H01L 27/11578 (2017.01)
[IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!][IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!]
Applicants:
YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN/CN]; Room 7018, No.18, Huaguang Road, Guandong Science And Technology Industrial Park East Lake High-Tech Development Zone Wuhan, Hubei 430074, CN
Inventors:
LU, Zhenyu; CN
CHEN, Jun; CN
DAI, Xiaowang; CN
ZHU, Jifeng; CN
TAO, Qian; CN
HUANG, Yuru; CN
HU, Siping; CN
YAO, Lan; CN
XIAO, Lihong; CN
ZHENG, Aman; CN
BAO, Kun; CN
YANG, Haohao; CN
Agent:
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.; 10th Floor, Tower C, Beijing Global Trade Center 36 North Third Ring Road East, Dongcheng District Beijing 100013, CN
Priority Data:
201710750398.428.08.2017CN
Title (EN) STAIRCASE STRUCTURE FOR MEMORY DEVICE
(FR) STRUCTURE EN ESCALIER POUR DISPOSITIF DE MÉMOIRE
Abstract:
(EN) A semiconductor structure is disclosed. The semiconductor structure includes a staircase structure (800) disposed over a substrate (101). The staircase structure (800) includes a plurality of layer stacks, where each layer stack is made of a first material layer (502) over a portion of a second material layer (840). The staircase structure (800) further includes a plurality of landing pads (820), where each landing pad (820) is disposed over another portion of the second material layer (840) of a respective layer stack.
(FR) L'invention concerne une structure semi-conductrice. La structure semi-conductrice inclut une structure en escalier (800) dispose au-dessus d'un substrat (101). La structure en escalier (800) inclut une pluralité d'empilements de couches, chaque empilement de couches étant constitué d'une première couche de matériau (502) au-dessus d'une partie d'une deuxième couche de matériau (840). La structure en escalier (800) inclut en outre une pluralité de pastilles de connexion (820), chaque pastille de connexion (820) étant disposée au-dessus d'une autre partie d'une deuxième couche de matériau (840) d'un empilement de couches respectif.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)