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1. (WO2019042071) METHOD TO IMPROVE CHANNEL HOLE UNIFORMITY OF THREE-DIMENSIONAL MEMORY DEVICE
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Pub. No.: WO/2019/042071 International Application No.: PCT/CN2018/098327
Publication Date: 07.03.2019 International Filing Date: 02.08.2018
IPC:
H01L 27/1157 (2017.01)
[IPC code unknown for H01L 27/1157]
Applicants:
YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN/CN]; Room 7018, No.18, Huaguang Road, Guandong Science and Technology Industrial Park East Lake High-Tech Development Zone Wuhan, Hubei 430074, CN
Inventors:
XIAO, Li Hong; CN
TAO, Qian; CN
HU, Yushi; CN
CHENG, XiaoTian; CN
XU, Jian; CN
YANG, Haohao; CN
PU, Yue Qiang; CN
DONG, Jin Wen; CN
Agent:
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.; 10th Floor, Tower C, Beijing Global Trade Center 36 North Third Ring Road East, Dongcheng District Beijing 100013, CN
Priority Data:
201710775876.731.08.2017CN
Title (EN) METHOD TO IMPROVE CHANNEL HOLE UNIFORMITY OF THREE-DIMENSIONAL MEMORY DEVICE
(FR) PROCÉDÉ D'AMÉLIORATION DE L'UNIFORMITÉ DES TROUS DE CANAL D'UN DISPOSITIF DE MÉMOIRE TRIDIMENSIONNELLE
Abstract:
(EN) Methods and structures of a three-dimensional memory device are disclosed. In an example, a method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.
(FR) Cette invention concerne des procédés et des structures d'un dispositif de mémoire tridimensionnelle. Selon un exemple, un procédé de formation d'un dispositif de mémoire tridimensionnelle consiste à disposer une couche de matériau sur un substrat, former une pluralité de trous de formation de canal et une pluralité de trous sacrificiels autour de la pluralité de trous de formation de canal dans une région de formation de réseau de la couche de matériau, et former une pluralité de canaux semi-conducteurs sur la base des trous de formation de canal et d'au moins une fente de ligne de grille (GLS) sur la base d'au moins l'un de la pluralité de trous sacrificiels. Un emplacement de la/des fente(s) GLS chevauche le(s) trou(s) sacrificiel(s) de la pluralité de trous sacrificiels.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)