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1. WO2019042071 - METHOD TO IMPROVE CHANNEL HOLE UNIFORMITY OF THREE-DIMENSIONAL MEMORY DEVICE

Publication Number WO/2019/042071
Publication Date 07.03.2019
International Application No. PCT/CN2018/098327
International Filing Date 02.08.2018
IPC
H01L 27/1157 2017.01
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11568characterised by the memory core region
1157with cell select transistors, e.g. NAND
CPC
H01L 27/11565
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11565characterised by the top-view layout
H01L 27/1157
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11568characterised by the memory core region
1157with cell select transistors, e.g. NAND
H01L 27/11578
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
H01L 27/11582
HELECTRICITY
01BASIC ELECTRIC ELEMENTS
LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
04the substrate being a semiconductor body
10including a plurality of individual components in a repetitive configuration
105including field-effect components
112Read-only memory structures ; [ROM] and multistep manufacturing processes therefor
115Electrically programmable read-only memories; Multistep manufacturing processes therefor
11563with charge-trapping gate insulators, e.g. MNOS or NROM
11578characterised by three-dimensional arrangements, e.g. with cells on different height levels
1158with source and drain on different levels, e.g. with sloping channels
11582the channels comprising vertical portions, e.g. U-shaped channels
Applicants
  • YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN]/[CN]
Inventors
  • XIAO, Li Hong
  • TAO, Qian
  • HU, Yushi
  • CHENG, XiaoTian
  • XU, Jian
  • YANG, Haohao
  • PU, Yue Qiang
  • DONG, Jin Wen
Agents
  • NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.
Priority Data
201710775876.731.08.2017CN
Publication Language English (EN)
Filing Language English (EN)
Designated States
Title
(EN) METHOD TO IMPROVE CHANNEL HOLE UNIFORMITY OF THREE-DIMENSIONAL MEMORY DEVICE
(FR) PROCÉDÉ D'AMÉLIORATION DE L'UNIFORMITÉ DES TROUS DE CANAL D'UN DISPOSITIF DE MÉMOIRE TRIDIMENSIONNELLE
Abstract
(EN)
Methods and structures of a three-dimensional memory device are disclosed. In an example, a method for forming a three-dimensional memory device includes disposing a material layer over a substrate, forming a plurality of channel-forming holes and a plurality of sacrificial holes around the plurality of channel-forming holes in an array-forming region of the material layer, and forming a plurality of semiconductor channels based on the channel-forming holes and at least one gate line slit (GLS) based on at least one of the plurality of sacrificial holes. A location of the at least one GLS overlaps with the at least one of the plurality of sacrificial holes.
(FR)
Cette invention concerne des procédés et des structures d'un dispositif de mémoire tridimensionnelle. Selon un exemple, un procédé de formation d'un dispositif de mémoire tridimensionnelle consiste à disposer une couche de matériau sur un substrat, former une pluralité de trous de formation de canal et une pluralité de trous sacrificiels autour de la pluralité de trous de formation de canal dans une région de formation de réseau de la couche de matériau, et former une pluralité de canaux semi-conducteurs sur la base des trous de formation de canal et d'au moins une fente de ligne de grille (GLS) sur la base d'au moins l'un de la pluralité de trous sacrificiels. Un emplacement de la/des fente(s) GLS chevauche le(s) trou(s) sacrificiel(s) de la pluralité de trous sacrificiels.
Also published as
Latest bibliographic data on file with the International Bureau