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Pub. No.: WO/2019/042058 International Application No.: PCT/CN2018/097723
Publication Date: 07.03.2019 International Filing Date: 30.07.2018
H01L 27/1157 (2017.01) ,H01L 27/11578 (2017.01)
[IPC code unknown for H01L 27/1157][IPC code unknown for ERROR IPC Code incorrect: invalid subgroup (0=>999999)!]
YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN/CN]; Room 7018, No.18, Huaguang Road, Guandong Science and Technology Industrial Park East Lake High-Tech Development Zone Wuhan, Hubei 430074, CN
CHEN, Ziqi; CN
WU, Guanping; CN
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.; 10th Floor, Tower C, Beijing Global Trade Center 36 North Third Ring Road East, Dongcheng District Beijing 100013, CN
Priority Data:
(EN) A method for forming a 3D memory device is disclosed. The method includes: forming an alternating dielectric stack including multiple first dielectric layers and second dielectric layers on a substrate; forming a channel hole penetrating the alternating dielectric stack, a first diameter of a lower portion of the channel hole being smaller than a second diameter of an upper portion of the channel hole; forming a channel structure including a functional layer in the channel hole, the functional layer including a storage layer; forming an electrode plug in the upper portion of the channel hole; replacing the storage layer in the functional layer in the upper portion of the channel hole with a second insulating layer; and replacing the second dielectric layers in the alternating dielectric stack with conductive layers.
(FR) L'invention concerne un procédé de formation d'un dispositif de mémoire 3D. Le procédé consiste : à former un empilement diélectrique alterné comprenant de multiples premières et secondes couches diélectriques sur un substrat ; à former un trou de canal pénétrant dans l'empilement diélectrique alterné, un premier diamètre d'une partie inférieure du trou de canal étant inférieur à un second diamètre d'une partie supérieure du trou de canal ; à former une structure de canal comprenant une couche fonctionnelle dans le trou de canal, la couche fonctionnelle comprenant une couche de stockage ; à former une fiche d'électrode dans la partie supérieure du trou de canal ; à remplacer la couche de stockage dans la couche fonctionnelle dans la partie supérieure du trou de canal par une seconde couche isolante ; et à remplacer les secondes couches diélectriques dans l'empilement diélectrique alterné par des couches conductrices.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)