Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019042011) ARRAY SUBSTRATE AND PREPARATION METHOD THEREFOR, DRIVE METHOD, AND DISPLAY APPARATUS
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/042011 International Application No.: PCT/CN2018/094614
Publication Date: 07.03.2019 International Filing Date: 05.07.2018
IPC:
H01L 27/12 (2006.01) ,H01L 21/77 (2017.01) ,G09G 3/3208 (2016.01) ,G09G 3/36 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
[IPC code unknown for G09G 3/3208]
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
34
by control of light from an independent source
36
using liquid crystals
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No. 10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
重庆京东方光电科技有限公司 CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; 中国重庆市 北碚区水土高新技术产业园云汉大道7号 No.7 Yunhan Rd. Shuitu Hi-Tech Industrial Zone, Beibei District Chongqing 400714, CN
Inventors:
陈虞龙 CHEN, Yulong; CN
王念念 WANG, Niannian; CN
熊永 XIONG, Yong; CN
张祥 ZHANG, Xiang; CN
Agent:
中国专利代理(香港)有限公司 CHINA PATENT AGENT (H.K.) LTD.; 中国香港特别行政区 湾仔港湾道23号鹰君中心22号楼 22/F, Great Eagle Centre 23 Harbour Road, Wanchai Hong Kong, CN
Priority Data:
201710765829.430.08.2017CN
Title (EN) ARRAY SUBSTRATE AND PREPARATION METHOD THEREFOR, DRIVE METHOD, AND DISPLAY APPARATUS
(FR) SUBSTRAT DE RÉSEAU ET SON PROCÉDÉ DE PRÉPARATION, PROCÉDÉ DE COMMANDE ET DISPOSITIF D'AFFICHAGE
(ZH) 阵列基板及其制备方法、驱动方法、显示装置
Abstract:
(EN) Disclosed in the embodiments of the present application are an array substrate and a preparation method therefor, a drive method, and a display apparatus. The array substrate comprises a plurality of gate lines and a plurality of data lines intersecting in the direction of extension, a plurality of pixel units limited by the plurality of gate lines and the plurality of data lines, and a plurality of auxiliary electrode lines alternately arranged with the gate lines. Each pixel unit comprises a first transistor, a second transistor, and a pixel electrode. The array substrate also comprises a third transistor between each gate line and the adjacent auxiliary electrode line, a control electrode of the third transistor being in electrical communication with the data line, a first electrode of the third transistor being in electrical communication with the gate line, and a second electrode of the third transistor being in electrical communication with the auxiliary electrode line.
(FR) La présente invention concerne, selon les modes de réalisation, un substrat de réseau et son procédé de préparation, un procédé de commande ainsi qu'un dispositif d'affichage. Le substrat de réseau comprend une pluralité de lignes de grille et une pluralité de lignes de données se croisant dans la direction d'extension, une pluralité d'unités de pixels limitées par la pluralité de lignes de grille et la pluralité de lignes de données, et une pluralité de lignes d'électrodes auxiliaires disposées en alternance avec les lignes de grille. Chaque unité de pixel comprend un premier transistor, un second transistor et une électrode de pixel. Le substrat de réseau comprend également un troisième transistor entre chaque ligne de grille et la ligne d'électrode auxiliaire adjacente, une électrode de commande du troisième transistor étant en communication électrique avec la ligne de données, une première électrode du troisième transistor étant en communication électrique avec la ligne de grille, et une seconde électrode du troisième transistor étant en communication électrique avec la ligne d'électrode auxiliaire.
(ZH) 本公开实施例提供一种阵列基板及其制备方法、驱动方法、显示装置。该阵列基板包括延伸方向相互交叉的多条栅线和多条数据线、由所述多条栅线和所述多条数据线限定的多个像素单元,以及与所述栅线交替排列的多条辅助电极线。每个像素单元包括第一晶体管、第二晶体管和像素电极。所述阵列基板还包括设置在每一条栅线和与其相邻的一条辅助电极线之间的第三晶体管,所述第三晶体管的控制极与数据线电连接,所述第三晶体管的第一极与所述栅线电连接,并且所述第三晶体管的第二极与所述辅助电极线电连接。
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)