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1. (WO2019041957) METHOD FOR FORMING THREE-DIMENSIONAL INTEGRATED WIRING STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF
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Pub. No.: WO/2019/041957 International Application No.: PCT/CN2018/090475
Publication Date: 07.03.2019 International Filing Date: 08.06.2018
IPC:
H01L 21/768 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
71
Manufacture of specific parts of devices defined in group H01L21/7086
768
Applying interconnections to be used for carrying current between separate components within a device
Applicants:
YANGTZE MEMORY TECHNOLOGIES CO., LTD. [CN/CN]; Room 7018, No.18, Huaguang Road, Guandong Science And Technology Industrial Park East Lake High-Tech Development Zone Wuhan, Hubei 430074, CN
Inventors:
ZHU, Jifeng; CN
CHEN, Jun; CN
HU, Si Ping; CN
LU, Zhenyu; CN
Agent:
NTD UNIVATION INTELLECTUAL PROPERTY AGENCY LTD.; 10th Floor, Tower C, Beijing Global Trade Center 36 North Third Ring Road East Dongcheng District Beijing 100013, CN
Priority Data:
201710775896.431.08.2017CN
Title (EN) METHOD FOR FORMING THREE-DIMENSIONAL INTEGRATED WIRING STRUCTURE AND SEMICONDUCTOR STRUCTURE THEREOF
(FR) PROCÉDÉ DE FORMATION D'UNE STRUCTURE DE CÂBLAGE INTÉGRÉ TRIDIMENSIONNELLE ET STRUCTURE SEMI-CONDUCTRICE ASSOCIÉE
Abstract:
(EN) Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming an insulating layer on a front side of a first substrate; forming a semiconductor layer on a front side of the insulating layer; patterning the semiconductor layer to expose at least a portion of a surface of the insulating layer; forming a plurality of semiconductor structures over the front side of the first substrate, wherein the semiconductor structures include a plurality of conductive contacts and a first conductive layer; joining a second substrate with the semiconductor structures; performing a thinning process on a backside of the first substrate to expose the insulating layer and one end of the plurality of conductive contacts; and forming a conductive wiring layer on the exposed insulating layer.
(FR) L'invention concerne des modes de réalisation de procédés et de structures pour former une structure de câblage intégré 3D. Le procédé peut comprendre la formation d'une couche isolante sur un côté avant d'un premier substrat; la formation d'une couche semi-conductrice sur un côté avant de la couche isolante; la formation de motifs sur la couche semi-conductrice pour exposer au moins une partie d'une surface de la couche isolante; la formation d'une pluralité de structures semi-conductrices sur le côté avant du premier substrat, les structures semi-conductrices comprenant une pluralité de contacts conducteurs et une première couche conductrice; la jonction d'un second substrat aux structures semi-conductrices; la réalisation d'un processus d'amincissement sur un coté arrière du premier substrat pour exposer la couche isolante et une extrémité de la pluralité de contacts conducteurs; et la formation d'une couche de câblage conductrice sur la couche isolante exposée.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)