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1. (WO2019041829) THIN FILM TRANSISTOR AND MANUFACTURING METHOD, DISPLAY SUBSTRATE AND MANUFACTURING METHOD, AND DISPLAY DEVICE
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Pub. No.: WO/2019/041829 International Application No.: PCT/CN2018/083535
Publication Date: 07.03.2019 International Filing Date: 18.04.2018
IPC:
H01L 27/12 (2006.01) ,H01L 29/786 (2006.01) ,H01L 29/423 (2006.01) ,H01L 21/336 (2006.01) ,H01L 27/32 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
423
not carrying the current to be rectified, amplified or switched
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
28
including components using organic materials as the active part, or using a combination of organic materials with other materials as the active part
32
with components specially adapted for light emission, e.g. flat-panel displays using organic light-emitting diodes
Applicants:
京东方科技集团股份有限公司 BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; 中国北京市 朝阳区酒仙桥路10号 No.10 Jiuxianqiao Rd., Chaoyang District Beijing 100015, CN
Inventors:
刘威 LIU, Wei; CN
Agent:
中科专利商标代理有限责任公司 CHINA SCIENCE PATENT & TRADEMARK AGENT LTD.; 中国北京市 海淀区西三环北路87号4-1105室 Suite 4-1105, No. 87, West 3rd Ring North Rd., Haidian District Beijing 100089, CN
Priority Data:
201710778593.831.08.2017CN
Title (EN) THIN FILM TRANSISTOR AND MANUFACTURING METHOD, DISPLAY SUBSTRATE AND MANUFACTURING METHOD, AND DISPLAY DEVICE
(FR) TRANSISTOR À COUCHES MINCES ET PROCÉDÉ DE FABRICATION, SUBSTRAT D'AFFICHAGE ET PROCÉDÉ DE FABRICATION, ET DISPOSITIF D'AFFICHAGE
(ZH) 薄膜晶体管及制作方法、显示基板及制作方法、显示装置
Abstract:
(EN) Provided is a thin film transistor and manufacturing method, a display substrate and manufacturing method, and a display device. A thin film transistor of an embodiment of the present disclosure comprises an active layer pattern provided on a substrate, a gate electrode insulating pattern provided on the active layer pattern, and a gate electrode provided on the gate electrode insulating pattern. Between the gate electrode and the gate electrode insulating pattern is provided a conducting pattern electrically connected to the gate electrode. The conducting pattern is superimposed on the gate electrode insulating pattern in an orthographic projection thereof on the substrate.
(FR) L'invention concerne un transistor à couches minces et un procédé de fabrication, un substrat d'affichage et un procédé de fabrication, et un dispositif d'affichage. Un transistor à couches minces selon un mode de réalisation de la présente invention comprend un motif de couche active disposé sur un substrat, un motif d'isolation d'électrode de grille disposé sur le motif de couche active, et une électrode de grille disposée sur le motif d'isolation d'électrode de grille. Entre l'électrode de grille et le motif d'isolation d'électrode de grille est disposé un motif conducteur connecté électriquement à l'électrode de grille. Le motif conducteur est superposé sur le motif d'isolation d'électrode de grille dans une projection orthographique de celui-ci sur le substrat.
(ZH) 提供了一种薄膜晶体管及制作方法、显示基板及制作方法、显示装置。本公开实施例的薄膜晶体管包括设置在衬底基板上的有源层图案、设置在有源层图案上的栅极绝缘图案,以及设置在栅极绝缘图案上的栅极;栅极与栅极绝缘图案之间设置有导电图案,导电图案与栅极电连接;导电图案与栅极绝缘图案在衬底基板上的正投影重合。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)