Some content of this application is unavailable at the moment.
If this situation persist, please contact us atFeedback&Contact
1. (WO2019041742) ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/041742 International Application No.: PCT/CN2018/074123
Publication Date: 07.03.2019 International Filing Date: 25.01.2018
IPC:
H01L 27/12 (2006.01) ,H01L 21/77 (2017.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District, Beijing 100015, CN
Inventors:
SONG, Zhen; CN
WANG, Guoying; CN
Agent:
TEE&HOWE INTELLECTUAL PROPERTY ATTORNEYS; Yuan CHEN 10th Floor, Tower D Minsheng Financial Center, 28 Jianguomennei Avenue Dongcheng District, Beijing 100005, CN
Priority Data:
201710778807.131.08.2017CN
Title (EN) ARRAY SUBSTRATE, DISPLAY APPARATUS, AND METHOD OF FABRICATING ARRAY SUBSTRATE
(FR) SUBSTRAT DE MATRICE, APPAREIL D'AFFICHAGE ET PROCÉDÉ DE FABRICATION DU SUBSTRAT DE MATRICE
Abstract:
(EN) The present application discloses an array substrate having a plurality of subpixel areas. The array substrate includes a base substrate; a plurality of first thin film transistors on the base substrate, each of which being in one of the plurality of subpixel areas; and a plurality of capacitor electrodes, each of which being in one of the plurality of subpixel areas. Each of the plurality of first thin film transistors includes a first active layer, a first gate electrode, a first source electrode, and a first drain electrode. The first active layer includes a first semi-conductive channel part, a first conductive part electrically connected to the first drain electrode, and a second conductive part electrically connected to the first source electrode. Each of the plurality of capacitor electrodes, the insulating layer, and the first conductive part constitute a first storage capacitor in one of the plurality of subpixel areas.
(FR) La présente invention concerne un substrat de matrice comportant une pluralité de zones de sous-pixels. Le substrat de matrice comprend un substrat de base; une pluralité de premiers transistors à film mince sur le substrat de base, chacun d'eux étant dans l'une des zones de la pluralité de zones de sous-pixels; et une pluralité d'électrodes de condensateur, chacune d'elles se trouvant dans l'une des zones de la pluralité de zones de sous-pixels. Chaque transistor de la pluralité de premiers transistors à film mince comprend une première couche active, une première électrode de grille, une première électrode de source et une première électrode de drain. La première couche active comprend une première partie canal semi-conduceur, une première partie conductrice connectée électriquement à la première électrode de drain, et une seconde partie conductrice connectée électriquement à la première électrode de source. Chaque électrode de la pluralité d'électrodes de condensateur, la couche isolante et la première partie conductrice constituent un premier condensateur de stockage dans l'une des zones de la pluralité de zones de sous-pixels.
front page image
Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)