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1. (WO2019041552) MANUFACTURING METHOD FOR TFT SUBSTRATE AND MANUFACTURING METHOD FOR TFT DISPLAY DEVICE
Latest bibliographic data on file with the International Bureau    Submit observation

Pub. No.: WO/2019/041552 International Application No.: PCT/CN2017/109828
Publication Date: 07.03.2019 International Filing Date: 08.11.2017
IPC:
H01L 21/77 (2017.01) ,H01L 27/12 (2006.01) ,H01L 21/3213 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
70
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in or on a common substrate or of specific parts thereof; Manufacture of integrated circuit devices or of specific parts thereof
77
Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
27
Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
02
including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
12
the substrate being other than a semiconductor body, e.g. an insulating body
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
30
Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20-H01L21/26142
31
to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After-treatment of these layers; Selection of materials for these layers
3205
Deposition of non-insulating-, e.g. conductive- or resistive-, layers, on insulating layers; After-treatment of these layers
321
After-treatment
3213
Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
Applicants:
武汉华星光电半导体显示技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD. [CN/CN]; 中国湖北省武汉市 东湖新技术开发区高新大道666号光谷生物创新园C5栋305室 305 Room, Building C5 Biolake of Optics Valley, No. 666 Gaoxin Avenue Wuhan East Lake High-Tech Development Zone Wuhan, Hubei 430079, CN
Inventors:
李松杉 LI, Songshan; CN
Agent:
深圳翼盛智成知识产权事务所(普通合伙) ESSEN PATENT & TRADEMARK AGENCY; 中国广东省深圳市 福田区深南大道6021号喜年中心A座1709-1711 Hailrun Complex Block A Room 1709-1711 No. 6021 Shennan Blvd., Futian District Shenzhen, Guangdong 518040, CN
Priority Data:
201710749034.428.08.2017CN
Title (EN) MANUFACTURING METHOD FOR TFT SUBSTRATE AND MANUFACTURING METHOD FOR TFT DISPLAY DEVICE
(FR) PROCÉDÉ DE FABRICATION DE SUBSTRAT DE TFT ET PROCÉDÉ DE FABRICATION DE DISPOSITIF D'AFFICHAGE TFT
(ZH) TFT基板的制作方法及TFT显示装置的制作方法
Abstract:
(EN) A manufacturing method for a TFT substrate and a manufacturing method for a TFT display device, comprising the steps of: providing a base substrate (20); forming a source/drain metal layer (21) on the base substrate (20); depositing a photoresist film (22) on the source/drain metal layer (21), and etching the photoresist film (22) to form a required pattern; removing a metal oxide (24) on the surface of the source/drain metal layer (21) using gas BCl3; and etching the source/drain metal layer (21) using gasCl2 and BCl3.
(FR) Un procédé de fabrication d'un substrat de transistor à couches minces (TFT) et un procédé de fabrication d'un dispositif d'affichage TFT, comprenant les étapes consistant à : fournir un substrat de base (20) ; former une couche métallique de source/drain (21) sur le substrat de base (20) ; déposer un film de résine photosensible (22) sur la couche métallique de source/drain (21), et graver le film de résine photosensible (22) pour former un motif requis ; retirer un oxyde métallique (24) à la surface de la couche métallique de source/drain (21) à l'aide du gaz BCl3 ; et à graver la couche métallique de source/drain (21) à l'aide des gaz Cl2 et BCl3.
(ZH) 一种TFT基板的制作方法及一种TFT显示装置的制作方法,包括步骤:提供一衬底基板(20);在衬底基板(20)上形成源漏极金属层(21);在源漏极金属层(21)上沉积一层光刻胶薄膜(22),在光刻胶薄膜(22)上蚀刻所需的图案;采用BCl 3气体除掉源漏极金属层(21)表面的金属氧化物(24);采用Cl 2气体和BCl 3气体对源漏极金属层(21)进行蚀刻。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)