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1. (WO2019041543) THIN FILM TRANSISTOR STRUCTURE AND AMOLED DRIVING CIRCUIT
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Pub. No.: WO/2019/041543 International Application No.: PCT/CN2017/109494
Publication Date: 07.03.2019 International Filing Date: 06.11.2017
IPC:
H01L 29/786 (2006.01) ,G09G 3/3233 (2016.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
[IPC code unknown for G09G 3/3233]
Applicants:
深圳市华星光电半导体显示技术有限公司 SHENZHEN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD. [CN/CN]; 中国广东省深圳市 光明新区公明街道塘明大道9-2号 No.9-2,Tangming Road Gongming Street, Guangming New District Shenzhen, Guangdong 518000, CN
Inventors:
余明爵 YU, Mingjue; CN
徐源竣 HSU, Yuan-jun; CN
Agent:
深圳翼盛智成知识产权事务所(普通合伙) ESSEN PATENT & TRADEMARK AGENCY; 中国广东省深圳市 福田区深南大道6021号喜年中心A座1709-1711 Hailrun Complex Block A Room 1709-1711 No. 6021 Shennan Blvd, Futian District Shenzhen, Guangdong 518040, CN
Priority Data:
201710784792.X04.09.2017CN
Title (EN) THIN FILM TRANSISTOR STRUCTURE AND AMOLED DRIVING CIRCUIT
(FR) STRUCTURE DE TRANSISTOR À COUCHES MINCES ET CIRCUIT D'ATTAQUE AMOLED
(ZH) 薄膜晶体管结构及AMOLED驱动电路
Abstract:
(EN) A thin film transistor structure, comprising a glass substrate (11), a buffer layer (12), a metal oxide semiconductor layer (13), and a gate insulating layer (15); wherein a shading metal layer (1A) is further provided between the glass substrate (11) and the buffer layer (12); a projection area of the gate metal layer (15) in a plane where the glass substrate (11) is located is aligned with a projection area of the shading metal layer (1A) in the plane where the glass substrate (11) is located; and the projection area of the shading metal layer (1A) in the plane where the glass substrate (11) is located covers a projection area of the metal oxide semiconductor layer (13) of a channel area (133) in the plane where the glass substrate (11) is located.
(FR) L'invention concerne une structure de transistor à couches minces, comprenant un substrat de verre (11), une couche tampon (12), une couche semi-conductrice d'oxyde métallique (13), et une couche d'isolation de grille (15) ; une couche métallique d'ombrage (1A) est en outre disposée entre le substrat de verre (11) et la couche tampon (12) ; une zone de projection de la couche métallique de grille (15) dans un plan où le substrat de verre (11) est situé est alignée avec une zone de projection de la couche métallique d'ombrage (1A) dans le plan où se trouve le substrat de verre (11) ; et la zone de projection de la couche métallique d'ombrage (1A) dans le plan où se trouve le substrat de verre (11) recouvre une zone de projection de la couche semi-conductrice d'oxyde métallique (13) d'une zone de canal (133) dans le plan où se trouve le substrat de verre (11).
(ZH) 一种薄膜晶体管结构,其包括玻璃基板(11)、缓冲层(12)、金属氧化物半导体层(13)以及栅极金属层(15);其中玻璃基板(11)和缓冲层(12)之间还设置有遮光金属层(1A),栅极金属层(15)在玻璃基板(11)所在平面的投影区域对齐遮光金属层(1A)在玻璃基板(11)所在平面的投影区域,遮光金属层(1A)在玻璃基板(11)所在平面的投影区域覆盖沟道区域(133)的金属氧化物半导体层(13)在玻璃基板(11)所在平面的投影区域。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)