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1. (WO2019041387) THIN-FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR, AND ARRAY SUBSTRATE
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Pub. No.: WO/2019/041387 International Application No.: PCT/CN2017/101973
Publication Date: 07.03.2019 International Filing Date: 15.09.2017
IPC:
H01L 29/786 (2006.01) ,H01L 29/06 (2006.01) ,H01L 29/41 (2006.01) ,H01L 21/336 (2006.01)
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
66
Types of semiconductor device
68
controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified, or switched
76
Unipolar devices
772
Field-effect transistors
78
with field effect produced by an insulated gate
786
Thin-film transistors
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
02
Semiconductor bodies
06
characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
29
Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having at least one potential-jump barrier or surface barrier; Capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof
40
Electrodes
41
characterised by their shape, relative sizes or dispositions
H ELECTRICITY
01
BASIC ELECTRIC ELEMENTS
L
SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
21
Processes or apparatus specially adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
02
Manufacture or treatment of semiconductor devices or of parts thereof
04
the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
18
the devices having semiconductor bodies comprising elements of the fourth group of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
334
Multistep processes for the manufacture of devices of the unipolar type
335
Field-effect transistors
336
with an insulated gate
Applicants:
武汉华星光电半导体显示技术有限公司 WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD. [CN/CN]; 中国湖北省武汉市 东湖新技术开发区高新大道666号光谷生物创新园C5栋305室 305 Room, Building C5, Biolake of Optics Valley, No.666 Gaoxin Avenue,Wuhan East Lake High-tech Development Zone Wuhan, Hubei 430070, CN
Inventors:
卜呈浩 BU, Chenghao; CN
Agent:
深圳市德力知识产权代理事务所 COMIPS INTELLECTUAL PROPERTY OFFICE; 中国广东省深圳市 福田区上步中路深勘大厦15E Room 15E Shenkan Building, Shangbu Zhong Road, Futian District Shenzhen, Guangdong 518028, CN
Priority Data:
201710752796.X28.08.2017CN
Title (EN) THIN-FILM TRANSISTOR AND MANUFACTURING METHOD THEREFOR, AND ARRAY SUBSTRATE
(FR) TRANSISTOR À COUCHES MINCES ET SON PROCÉDÉ DE FABRICATION , ET SUBSTRAT DE RÉSEAU
(ZH) 薄膜晶体管及其制作方法以及阵列基板
Abstract:
(EN) Provided are a thin-film transistor and a manufacturing method therefor, and an array substrate. According to the thin-film transistor, a spacing layer (5) is provided between a source electrode (4) and a drain electrode (6), and an oxide semiconductor channel layer (7) as a vertical channel is provided at one side of the spacing layer (5) and the drain electrode (6) and is in contact with a part of an upper surface of the drain electrode (6), side surfaces of the drain electrode (6) and the spacing layer (5), and a part of the upper surface of the source electrode (4), the length of the channel being the thickness of the spacing layer (5). The length of the vertical channel can be reduced to be at a submicron scale by changing the thickness of the spacing layer (5), so that the size of the thin-film transistor can be significantly reduced and the pixel area is reduced; no short-channel effect occurs to the vertical channel, facilitating enhancing the electrical property of the thin-film transistor; a multi-layer hexagonal boron nitride thin film is used as a water-oxygen blocking layer (2), and a dual-layer graphene thin film is used as the source electrode (4) and the drain electrode (6), so that the bending proof performance of the thin-film transistor can be significantly improved.
(FR) L'invention concerne un transistor à couches minces et son procédé de fabrication, ainsi qu'un substrat de réseau. Selon le transistor à couches minces, une couche d'espacement (5) est disposée entre une électrode de source (4) et une électrode de drain (6), et une couche de canal semi-conducteur d'oxyde (7) en tant que canal vertical est disposée sur un côté de la couche d'espacement (5) et l'électrode de drain (6) et est en contact avec une partie d'une surface supérieure de l'électrode de drain (6), des surfaces latérales de l'électrode de drain (6) et de la couche d'espacement (5), et une partie de la surface supérieure de l'électrode de source (4), la longueur du canal étant l'épaisseur de la couche d'espacement (5). La longueur du canal vertical peut être réduite pour être à une échelle submicronique en changeant l'épaisseur de la couche d'espacement (5), de telle sorte que la taille du transistor à couches minces peut être significativement réduite et que la zone de pixel est réduite ; aucun effet de canal court ne se produit sur le canal vertical, ce qui facilite l'amélioration de la propriété électrique du transistor à couches minces ; un film mince de nitrure de bore hexagonal multicouche est utilisé en tant que couche de blocage d'eau-oxygène (2), et un film mince de graphène à double couche est utilisé en tant qu'électrode de source (4) et l'électrode de drain (6), de telle sorte que la performance de résistance à la flexion du transistor à couches minces peut être considérablement améliorée.
(ZH) 提供一种薄膜晶体管及其制作方法以及阵列基板。该薄膜晶体管在源极(4)与漏极(6)之间设置间隔层(5),在间隔层(5)与漏极(6)一侧设置接触部分漏极(6)上表面、漏极(6)与间隔层(5)的侧面、及部分源极(4)上表面的氧化物半导体沟道层(7)作为垂直沟道,沟道长度即间隔层(5)的厚度,可通过改变间隔层(5)的厚度将垂直沟道的长度降到亚微米量级,能够大幅减小薄膜晶体管的尺寸,减小像素面积;垂直沟道不会发生短沟道效应,有助于提高薄膜晶体管的电性;采用多层的六方氮化硼薄膜作为水氧阻隔层(2),采用双层石墨烯薄膜作为源极(4)与漏极(6),能够显著提高薄膜晶体管的耐弯折性。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Office (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (EPO) (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)