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1. WO2019041251 - CHIP DEVICE AND RELATED PRODUCT

Publication Number WO/2019/041251
Publication Date 07.03.2019
International Application No. PCT/CN2017/099991
International Filing Date 31.08.2017
Chapter 2 Demand Filed 22.01.2019
IPC
G06N 3/06 2006.01
GPHYSICS
06COMPUTING; CALCULATING OR COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
CPC
G06F 17/16
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
17Digital computing or data processing equipment or methods, specially adapted for specific functions
10Complex mathematical operations
16Matrix or vector computation ; , e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
G06F 9/3822
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3818Decoding for concurrent execution
3822Parallel decoding, e.g. parallel decode units
G06F 9/3885
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
FELECTRIC DIGITAL DATA PROCESSING
9Arrangements for program control, e.g. control units
06using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
30Arrangements for executing machine instructions, e.g. instruction decode
38Concurrent instruction execution, e.g. pipeline, look ahead
3885using a plurality of independent parallel functional units
G06N 3/0454
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
04Architectures, e.g. interconnection topology
0454using a combination of multiple neural nets
G06N 3/0481
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
04Architectures, e.g. interconnection topology
0481Non-linear activation functions, e.g. sigmoids, thresholds
G06N 3/063
GPHYSICS
06COMPUTING; CALCULATING; COUNTING
NCOMPUTER SYSTEMS BASED ON SPECIFIC COMPUTATIONAL MODELS
3Computer systems based on biological models
02using neural network models
06Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
063using electronic means
Applicants
  • 中科寒武纪科技股份有限公司 CAMBRICON TECHNOLOGIES CORPORATION LIMITED [CN]/[CN]
Inventors
  • 刘少礼 LIU, Shaoli
  • 陈天石 CHEN, Tianshi
  • 王秉睿 WANG, Bingrui
  • 张尧 ZHANG, Yao
Agents
  • 广州三环专利商标代理有限公司 SCIHEAD IP LAW FIRM
Priority Data
Publication Language Chinese (ZH)
Filing Language Chinese (ZH)
Designated States
Title
(EN) CHIP DEVICE AND RELATED PRODUCT
(FR) DISPOSITIF À PUCE ET PRODUIT ASSOCIÉ
(ZH) 芯片装置及相关产品
Abstract
(EN)
A chip device and a related product. The chip device comprises a main unit and multiple basic units communicating with the main unit. Functions of the main unit comprise: obtaining a data block to be computed and an operation instruction (S201); classifying, as a distributed data block or a broadcast data block on the basis of the operation instruction, the data block to be computed (S202); and splitting the distributed data block to obtain multiple basic data blocks, distributing the multiple basic data blocks to the multiple basic units, and broadcasting the broadcast data block to the multiple basic units (S203). Functions of the basic units comprise: performing an inner product operation on the basic data blocks and the broadcast data block to obtain an operation result and sending the operation result to the main unit (S204). The main unit processes the operation result to obtain the data block to be computed and an instruction result of the operation instruction (S205). The invention shortens processing time periods and has low power consumption.
(FR)
La présente invention concerne un dispositif à puce et un produit associé. Le dispositif à puce comprend une unité principale et de multiples unités de base communiquant avec l'unité principale. Les fonctions de l'unité principale comprennent : l'obtention d'un bloc de données à calculer et d'une instruction d'opération (S201); la classification, en tant que bloc de données réparti ou que bloc de données diffusé sur la base de l'instruction d'opération, du bloc de données à calculer (S202); et la division du bloc de données réparti pour obtenir de multiples blocs de données de base, la répartition des multiples blocs de données de base entre les multiples unités de base, et la diffusion du bloc de données diffusé aux multiples unités de base (S203). Les fonctions des unités de base comprennent : la mise en œuvre d'une opération de produit interne sur les blocs de données de base et le bloc de données diffusé pour obtenir un résultat d'opération et l'envoi du résultat de l'opération à l'unité principale (S204). L'unité principale traite le résultat de l'opération pour obtenir le bloc de données à calculer et un résultat d'instruction de l'instruction d'opération (S205). L'invention raccourcit les durées de traitement et présente une faible consommation d'énergie.
(ZH)
一种芯片装置以及相关产品,所述芯片装置包括:主单元以及多个与其通信的基本单元,主单元的功能包括:获取待计算的数据块以及运算指令(S201),依据该运算指令对所述待计算的数据块划分成分发数据块以及广播数据块(S202);对所述分发数据块进行拆分处理得到多个基本数据块,将所述多个基本数据块分发至所述多个基本单元,并将所述广播数据块广播至所述多个基本单元(S203)。基本单元的功能包括:对所述基本数据块与所述广播数据块执行内积运算得到运算结果,将所述运算结果发送至主单元(S204)。主单元对所述运算结果处理得到所述待计算的数据块以及运算指令的指令结果(S205)。具有计算处理时间段,能耗低的优点。
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