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1. (WO2019033682) CLOCK SIGNAL ANALYSIS METHOD
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/033682 International Application No.: PCT/CN2017/119624
Publication Date: 21.02.2019 International Filing Date: 29.12.2017
IPC:
G06F 17/50 (2006.01)
G PHYSICS
06
COMPUTING; CALCULATING; COUNTING
F
ELECTRIC DIGITAL DATA PROCESSING
17
Digital computing or data processing equipment or methods, specially adapted for specific functions
50
Computer-aided design
Applicants:
郑州云海信息技术有限公司 ZHENGZHOU YUNHAI INFORMATION TECHNOLOGY CO., LTD. [CN/CN]; 中国河南省郑州市 郑东新区心怡路278号基运投资大厦16层 16th Floor Jiyuntouzi Building No.278 Xinyi Road, Zheng Dong New District Zhengzhou, Henan 450018, CN
Inventors:
刘法志 LIU, Fazhi; CN
Agent:
北京集佳知识产权代理有限公司 UNITALEN ATTORNEYS AT LAW; 中国北京市 朝阳区建国门外大街22号赛特广场7层 7th Floor, Scitech Place No.22, Jian Guo Men Wai Ave., Chao Yang District Beijing 100004, CN
Priority Data:
201710695574.915.08.2017CN
Title (EN) CLOCK SIGNAL ANALYSIS METHOD
(FR) PROCÉDÉ D’ANALYSE DE SIGNAL D’HORLOGE
(ZH) 一种分析时钟信号的方法
Abstract:
(EN) Disclosed is a clock signal analysis method. The method comprises: S1, acquiring link structures where a clock signal is located; S2, extracting topological structures of all the link structures; S3, calculating, based on the obtained topological structures, the longest and shortest flight time of the clock signal; and S4, substituting the data obtained in step S3 into a formula about a setup time and a holding time, and determining, according to a calculation result, whether a problem exists in the clock signal of a system. According to the method, the clock signal is analysed from a design stage of a circuit board in order to ensure that a design scheme that is as sound as possible is obtained at the design stage, thereby preventing resource losses and reducing design costs.
(FR) La présente invention concerne un procédé d’analyse de signal d’horloge. Le procédé comprend : S1, l’acquisition de structures de liaison dans lesquelles est situé un signal d’horloge ; S2, l’extraction de structures topologiques de toutes les structures de liaison ; S3, le calcul, sur la base des structures topologiques obtenues, du plus long et du plus court temps de vol du signal d’horloge ; et S4, la substitution des données obtenues à l’étape S3 dans une formule liée à un temps d’établissement et à un temps de maintien, et le fait de déterminer, selon un résultat de calcul, si un problème existe dans le signal d’horloge d’un système. Selon le procédé, le signal d’horloge est analysé à partir d’une phase de conception d’une carte de circuit imprimé afin d’assurer qu’un schéma de conception, qui est aussi bon que possible, est obtenu lors de la phase de conception, ce qui prévient des pertes de ressources et réduit les coûts de conception.
(ZH) 一种分析Clock信号的方法,所述的方法包括:S1:获取Clock信号所在的链路结构;S2:提取所有链路结构的拓扑结构;S3:基于获得的拓扑结构,计算Clock信号的最大和最小飞行时间;S4:将步骤S3所得数据带入建立时间和保持时间的公式中,根据计算结果判断系统的Clock信号是否有问题。所述方法从电路板的设计阶段对Clock信号进行分析,确保在设计阶段获得尽可能完善的设计方案,避免资源损耗,降低设计成本。
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: Chinese (ZH)
Filing Language: Chinese (ZH)