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1. (WO2019033641) PIXEL CIRCUIT, DISPLAY PANEL, DRIVING METHOD THEREOF, AND A DISPLAY APPARATUS
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/033641 International Application No.: PCT/CN2017/115913
Publication Date: 21.02.2019 International Filing Date: 13.12.2017
IPC:
G09G 3/36 (2006.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
34
by control of light from an independent source
36
using liquid crystals
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No.10 Jiuxianqiao Rd., Chaoyang District, Beijing 100015, CN
ORDOS YUANSHENG OPTOELECTRONICS CO., LTD. [CN/CN]; Ordos Equipment Manufacturing Base, Dongsheng District, Ordos, Inner Mongolia 017020, CN
Inventors:
LI, Fuqiang; CN
FAN, Jun; CN
Agent:
TEE&HOWE INTELLECTUAL PROPERTY ATTORNEYS; Yuan CHEN 10th Floor, Tower D, Minsheng Financial Center, 28 Jianguomennei Avenue, Dongcheng District, Beijing 100005, CN
Priority Data:
201710692677.X14.08.2017CN
Title (EN) PIXEL CIRCUIT, DISPLAY PANEL, DRIVING METHOD THEREOF, AND A DISPLAY APPARATUS
(FR) CIRCUIT DE PIXEL, PANNEAU D'AFFICHAGE, SON PROCÉDÉ D'ATTAQUE ET APPAREIL D'AFFICHAGE
Abstract:
(EN) A pixel circuit of a display panel includes a first latch-control sub-circuit (200) configured to provide a data signal under controls of a first scan signal, a latch sub-circuit (100) including a first inverter (110) having an input terminal (Q) coupled to receive the data signal and a second inverter (120), a second latch-control sub-circuit (600,700,800) configured to disconnect the second inverter (120) from the first inverter (110) to form an open circuit under controls of the first scan signal or form a latch loop under controls of a second scan signal to stabilize two voltage levels at the first output terminal (AQ) of the first inverter (110) and the second output terminal (O2) of the second output inverter (120), and an output sub-circuit (300) configured to switch connection between an output terminal and two reference voltage ports (FRP, XFRP) under controls of the two voltage levels alternatively.
(FR) La présente invention concerne un circuit de pixel d'un panneau d'affichage qui comprend un premier sous-circuit de commande de verrouillage (200) configuré pour fournir un signal de données sous la commande d'un premier signal de balayage, un sous-circuit de verrouillage (100) comprenant un premier onduleur (110) ayant une borne d'entrée (Q) couplée de manière à recevoir le signal de données et un second onduleur (120), un second sous-circuit de commande de verrouillage (600, 700, 800) configuré pour déconnecter le second onduleur (120) du premier onduleur (110) afin de former un circuit ouvert sous la commande du premier signal de balayage ou de former une boucle de verrouillage sous la commande d'un second signal de balayage pour stabiliser deux niveaux de tension au niveau de la première borne de sortie (AQ) du premier onduleur (110) et de la seconde borne de sortie (O2) du second onduleur de sortie (120), et un sous-circuit de sortie (300) configuré pour commuter une connexion entre une borne de sortie et deux ports de tension de référence (FRP, XFRP) sous la commande des deux niveaux de tension, de manière alternative.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)