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1. (WO2019033294) GATE DRIVER ON ARRAY CIRCUIT, PIXEL CIRCUIT OF AN AMOLED DISPLAY PANEL, AMOLED DISPLAY PANEL, AND METHOD OF DRIVING PIXEL CIRCUIT OF AMOLED DISPLAY PANEL
Latest bibliographic data on file with the International BureauSubmit observation

Pub. No.: WO/2019/033294 International Application No.: PCT/CN2017/097643
Publication Date: 21.02.2019 International Filing Date: 16.08.2017
IPC:
G09G 3/36 (2006.01) ,G09G 3/3225 (2016.01)
G PHYSICS
09
EDUCATING; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
G
ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
3
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
20
for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix
34
by control of light from an independent source
36
using liquid crystals
[IPC code unknown for G09G 3/3225]
Applicants:
BOE TECHNOLOGY GROUP CO., LTD. [CN/CN]; No. 10 Jiuxianqiao Rd., Chaoyang District, Beijing 100015, CN
HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD. [CN/CN]; Xinzhan Industrial Park, Hefei, Anhui 230012, CN
Inventors:
HU, Zuquan; CN
WANG, Xiping; CN
Agent:
TEE & HOWE INTELLECTUAL PROPERTY ATTORNEYS; CHEN, Yuan 10th Floor, Tower D, Minsheng Financial Center, 28 Jianguomennei Avenue, Dongcheng District, Beijing 100005, CN
Priority Data:
Title (EN) GATE DRIVER ON ARRAY CIRCUIT, PIXEL CIRCUIT OF AN AMOLED DISPLAY PANEL, AMOLED DISPLAY PANEL, AND METHOD OF DRIVING PIXEL CIRCUIT OF AMOLED DISPLAY PANEL
(FR) CIRCUIT DE PILOTE DE GRILLE SUR RÉSEAU, CIRCUIT DE PIXEL DE PANNEAU D'AFFICHAGE AMOLED, PANNEAU D'AFFICHAGE AMOLED ET PROCÉDÉ DE PILOTAGE DE CIRCUIT DE PIXEL DE PANNEAU D'AFFICHAGE AMOLED
Abstract:
(EN) A gate-driver-on-array (GOA) circuit includes N GOA units cascaded in series to generate N sets of driving signals. Each n-th GOA unit includes a first terminal configured to receive a high-level voltage, a second terminal configured to receive a low-level voltage, and a clock signal terminal configured to receive a clock signal, an input terminal and a reset terminal respectively configured to receive internal signals from two alternative GOA units in the series, a first output terminal configured to output a gate-driving signal, and a second output terminal configured to output a node voltage signal. Each n-th set of the N sets of driving signals includes a first driving signal being a gate-driving signal from a (n-1)-th GOA unit, a second driving signal being a gate-driving signal from a n-th GOA unit, and a third driving signal being a node voltage signal from the n-th GOA unit for driving an AMOLED pixel circuit.
(FR) Selon l'invention, un circuit de pilote de grille sur réseau (GOA) contient N unités GOA en cascade en série pour produire N ensembles de signaux de pilotage. Chaque n-ième unité GOA comprend une première borne configurée pour recevoir une tension de niveau haut, une deuxième borne configurée pour recevoir une tension de niveau bas, et une borne de signal d'horloge configurée pour recevoir un signal d'horloge, une borne d'entrée et une borne de réinitialisation configurées respectivement pour recevoir des signaux internes provenant de deux unités GOA alternatives dans la série, une première borne de sortie configurée pour fournir un signal de commande de grille, et une deuxième borne de sortie configurée pour fournir un signal de tension de nœud. Chaque n-ième ensemble des N ensembles de signaux de pilotage contient un premier signal de pilotage qui est un signal de pilotage de grille provenant d'une (n - 1)-ième unité GOA, un deuxième signal de pilotage étant un signal de pilotage de grille provenant d'une n-ième unité GOA, et un troisième signal de pilotage étant un signal de tension de nœud provenant de la n-ième unité GOA pour piloter un circuit de pixel AMOLED.
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Designated States: AE, AG, AL, AM, AO, AT, AU, AZ, BA, BB, BG, BH, BN, BR, BW, BY, BZ, CA, CH, CL, CN, CO, CR, CU, CZ, DE, DJ, DK, DM, DO, DZ, EC, EE, EG, ES, FI, GB, GD, GE, GH, GM, GT, HN, HR, HU, ID, IL, IN, IR, IS, JO, JP, KE, KG, KH, KN, KP, KR, KW, KZ, LA, LC, LK, LR, LS, LU, LY, MA, MD, ME, MG, MK, MN, MW, MX, MY, MZ, NA, NG, NI, NO, NZ, OM, PA, PE, PG, PH, PL, PT, QA, RO, RS, RU, RW, SA, SC, SD, SE, SG, SK, SL, SM, ST, SV, SY, TH, TJ, TM, TN, TR, TT, TZ, UA, UG, US, UZ, VC, VN, ZA, ZM, ZW
African Regional Intellectual Property Organization (ARIPO) (BW, GH, GM, KE, LR, LS, MW, MZ, NA, RW, SD, SL, ST, SZ, TZ, UG, ZM, ZW)
Eurasian Patent Organization (AM, AZ, BY, KG, KZ, RU, TJ, TM)
European Patent Office (AL, AT, BE, BG, CH, CY, CZ, DE, DK, EE, ES, FI, FR, GB, GR, HR, HU, IE, IS, IT, LT, LU, LV, MC, MK, MT, NL, NO, PL, PT, RO, RS, SE, SI, SK, SM, TR)
African Intellectual Property Organization (BF, BJ, CF, CG, CI, CM, GA, GN, GQ, GW, KM, ML, MR, NE, SN, TD, TG)
Publication Language: English (EN)
Filing Language: English (EN)